blob: 53ce88c6cdf5c829254a686776d3baa85b761da7 [file] [log] [blame]
Stefan Roese5fb692c2007-01-18 10:25:34 +01001/*
2 * Copyright (C) 2004 PaulReynolds@lhsolutions.com
3 *
4 * (C) Copyright 2007
5 * Stefan Roese, DENX Software Engineering, sr@denx.de.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <common.h>
27#include <asm/processor.h>
28#include <spd_sdram.h>
29#include <ppc4xx_enet.h>
Ben Warren10efa022008-08-31 20:37:00 -070030#include <netdev.h>
Stefan Roese5fb692c2007-01-18 10:25:34 +010031
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020032#ifdef CONFIG_SYS_INIT_SHOW_RESET_REG
Stefan Roese5fb692c2007-01-18 10:25:34 +010033void show_reset_reg(void);
34#endif
35
Wolfgang Denk1218abf2007-09-15 20:48:41 +020036DECLARE_GLOBAL_DATA_PTR;
37
Stefan Roese5fb692c2007-01-18 10:25:34 +010038int lcd_init(void);
39
40int board_early_init_f (void)
41{
42 unsigned long reg;
43 volatile unsigned int *GpioOdr;
44 volatile unsigned int *GpioTcr;
45 volatile unsigned int *GpioOr;
46
47 /*-------------------------------------------------------------------------+
48 | Initialize EBC CONFIG
49 +-------------------------------------------------------------------------*/
50 mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
51 EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
52 EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
53 EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_DEFAULT |
54 EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
55
56 /*-------------------------------------------------------------------------+
57 | 64MB FLASH. Initialize bank 0 with default values.
58 +-------------------------------------------------------------------------*/
59 mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(15) |
60 EBC_BXAP_BCE_DISABLE |
61 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) |
62 EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) |
63 EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED |
64 EBC_BXAP_BEM_WRITEONLY |
65 EBC_BXAP_PEN_DISABLED);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066 mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |
Stefan Roese5fb692c2007-01-18 10:25:34 +010067 EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_32BIT);
68
69 /*-------------------------------------------------------------------------+
70 | FPGA. Initialize bank 1 with default values.
71 +-------------------------------------------------------------------------*/
72 mtebc(pb1ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(5) |
73 EBC_BXAP_BCE_DISABLE |
74 EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) |
75 EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) |
76 EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED |
77 EBC_BXAP_BEM_WRITEONLY |
78 EBC_BXAP_PEN_DISABLED);
79 mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x41000000) |
80 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
81
82 /*-------------------------------------------------------------------------+
83 | LCM. Initialize bank 2 with default values.
84 +-------------------------------------------------------------------------*/
85 mtebc(pb2ap, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(64) |
86 EBC_BXAP_BCE_DISABLE |
87 EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) |
88 EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) |
89 EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED |
90 EBC_BXAP_BEM_WRITEONLY |
91 EBC_BXAP_PEN_DISABLED);
92 mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0x42000000) |
93 EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
94
95 /*-------------------------------------------------------------------------+
96 | TMP. Initialize bank 3 with default values.
97 +-------------------------------------------------------------------------*/
98 mtebc(pb3ap, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(128) |
99 EBC_BXAP_BCE_DISABLE |
100 EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) |
101 EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) |
102 EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED |
103 EBC_BXAP_BEM_WRITEONLY |
104 EBC_BXAP_PEN_DISABLED);
105 mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48000000) |
106 EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
107
108 /*-------------------------------------------------------------------------+
109 | Connector 4~7. Initialize bank 3~ 7 with default values.
110 +-------------------------------------------------------------------------*/
111 mtebc(pb4ap,0);
112 mtebc(pb4cr,0);
113 mtebc(pb5ap,0);
114 mtebc(pb5cr,0);
115 mtebc(pb6ap,0);
116 mtebc(pb6cr,0);
117 mtebc(pb7ap,0);
118 mtebc(pb7cr,0);
119
120 /*--------------------------------------------------------------------
121 * Setup the interrupt controller polarities, triggers, etc.
122 *-------------------------------------------------------------------*/
Stefan Roese5de85142008-06-26 17:36:39 +0200123 /*
124 * Because of the interrupt handling rework to handle 440GX interrupts
125 * with the common code, we needed to change names of the UIC registers.
126 * Here the new relationship:
127 *
128 * U-Boot name 440GX name
129 * -----------------------
130 * UIC0 UICB0
131 * UIC1 UIC0
132 * UIC2 UIC1
133 * UIC3 UIC2
134 */
Stefan Roese5fb692c2007-01-18 10:25:34 +0100135 mtdcr (uic1sr, 0xffffffff); /* clear all */
136 mtdcr (uic1er, 0x00000000); /* disable all */
Stefan Roese5de85142008-06-26 17:36:39 +0200137 mtdcr (uic1cr, 0x00000009); /* SMI & UIC1 crit are critical */
138 mtdcr (uic1pr, 0xfffffe13); /* per ref-board manual */
139 mtdcr (uic1tr, 0x01c00008); /* per ref-board manual */
Stefan Roese5fb692c2007-01-18 10:25:34 +0100140 mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
141 mtdcr (uic1sr, 0xffffffff); /* clear all */
142
143 mtdcr (uic2sr, 0xffffffff); /* clear all */
144 mtdcr (uic2er, 0x00000000); /* disable all */
145 mtdcr (uic2cr, 0x00000000); /* all non-critical */
Stefan Roese5de85142008-06-26 17:36:39 +0200146 mtdcr (uic2pr, 0xffffe0ff); /* per ref-board manual */
147 mtdcr (uic2tr, 0x00ffc000); /* per ref-board manual */
Stefan Roese5fb692c2007-01-18 10:25:34 +0100148 mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
149 mtdcr (uic2sr, 0xffffffff); /* clear all */
150
Stefan Roese5de85142008-06-26 17:36:39 +0200151 mtdcr (uic3sr, 0xffffffff); /* clear all */
152 mtdcr (uic3er, 0x00000000); /* disable all */
153 mtdcr (uic3cr, 0x00000000); /* all non-critical */
154 mtdcr (uic3pr, 0xffffffff); /* per ref-board manual */
155 mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */
156 mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */
157 mtdcr (uic3sr, 0xffffffff); /* clear all */
158
159 mtdcr (uic0sr, 0xfc000000); /* clear all */
160 mtdcr (uic0er, 0x00000000); /* disable all */
161 mtdcr (uic0cr, 0x00000000); /* all non-critical */
162 mtdcr (uic0pr, 0xfc000000); /* */
163 mtdcr (uic0tr, 0x00000000); /* */
164 mtdcr (uic0vr, 0x00000001); /* */
Stefan Roese5fb692c2007-01-18 10:25:34 +0100165
166 /* Enable two GPIO 10~11 and TraceA signal */
167 mfsdr(sdr_pfc0,reg);
168 reg |= 0x00300000;
169 mtsdr(sdr_pfc0,reg);
170
171 mfsdr(sdr_pfc1,reg);
172 reg |= 0x00100000;
173 mtsdr(sdr_pfc1,reg);
174
175 /* Set GPIO 10 and 11 as output */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176 GpioOdr = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x718);
177 GpioTcr = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x704);
178 GpioOr = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x700);
Stefan Roese5fb692c2007-01-18 10:25:34 +0100179
180 *GpioOdr &= ~(0x00300000);
181 *GpioTcr |= 0x00300000;
Wolfgang Denka4012392007-01-19 23:08:39 +0100182 *GpioOr |= 0x00300000;
Stefan Roese5fb692c2007-01-18 10:25:34 +0100183
184 return 0;
185}
186
187int misc_init_r(void)
188{
189 lcd_init();
190
191 return 0;
192}
193
194int checkboard (void)
195{
196 char *s = getenv ("serial#");
197
198 printf ("Board: Taishan - AMCC PPC440GX Evaluation Board");
199 if (s != NULL) {
200 puts (", serial# ");
201 puts (s);
202 }
203 putc ('\n');
204
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#ifdef CONFIG_SYS_INIT_SHOW_RESET_REG
Stefan Roese5fb692c2007-01-18 10:25:34 +0100206 show_reset_reg();
207#endif
208
209 return (0);
210}
211
Stefan Roese5fb692c2007-01-18 10:25:34 +0100212/*************************************************************************
213 * pci_pre_init
214 *
215 * This routine is called just prior to registering the hose and gives
216 * the board the opportunity to check things. Returning a value of zero
217 * indicates that things are bad & PCI initialization should be aborted.
218 *
219 * Different boards may wish to customize the pci controller structure
220 * (add regions, override default access routines, etc) or perform
221 * certain pre-initialization actions.
222 *
223 ************************************************************************/
Stefan Roese466fff12007-06-25 15:57:39 +0200224#if defined(CONFIG_PCI)
Stefan Roese5fb692c2007-01-18 10:25:34 +0100225int pci_pre_init(struct pci_controller * hose )
226{
227 unsigned long strap;
228
229 /*--------------------------------------------------------------------------+
230 * The ocotea board is always configured as the host & requires the
231 * PCI arbiter to be enabled.
232 *--------------------------------------------------------------------------*/
233 mfsdr(sdr_sdstp1, strap);
234 if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
235 printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
236 return 0;
237 }
238
239 return 1;
240}
Stefan Roese466fff12007-06-25 15:57:39 +0200241#endif /* defined(CONFIG_PCI) */
Stefan Roese5fb692c2007-01-18 10:25:34 +0100242
243/*************************************************************************
244 * pci_target_init
245 *
246 * The bootstrap configuration provides default settings for the pci
247 * inbound map (PIM). But the bootstrap config choices are limited and
248 * may not be sufficient for a given board.
249 *
250 ************************************************************************/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
Stefan Roese5fb692c2007-01-18 10:25:34 +0100252void pci_target_init(struct pci_controller * hose )
253{
Stefan Roese5fb692c2007-01-18 10:25:34 +0100254 /*--------------------------------------------------------------------------+
255 * Disable everything
256 *--------------------------------------------------------------------------*/
257 out32r( PCIX0_PIM0SA, 0 ); /* disable */
258 out32r( PCIX0_PIM1SA, 0 ); /* disable */
259 out32r( PCIX0_PIM2SA, 0 ); /* disable */
260 out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
261
262 /*--------------------------------------------------------------------------+
263 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
264 * options to not support sizes such as 128/256 MB.
265 *--------------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266 out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
Stefan Roese5fb692c2007-01-18 10:25:34 +0100267 out32r( PCIX0_PIM0LAH, 0 );
268 out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
269
270 out32r( PCIX0_BAR0, 0 );
271
272 /*--------------------------------------------------------------------------+
273 * Program the board's subsystem id/vendor id
274 *--------------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275 out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
276 out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
Stefan Roese5fb692c2007-01-18 10:25:34 +0100277
278 out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
279}
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
Stefan Roese5fb692c2007-01-18 10:25:34 +0100281
282/*************************************************************************
283 * is_pci_host
284 *
285 * This routine is called to determine if a pci scan should be
286 * performed. With various hardware environments (especially cPCI and
287 * PPMC) it's insufficient to depend on the state of the arbiter enable
288 * bit in the strap register, or generic host/adapter assumptions.
289 *
290 * Rather than hard-code a bad assumption in the general 440 code, the
291 * 440 pci code requires the board to decide at runtime.
292 *
293 * Return 0 for adapter mode, non-zero for host (monarch) mode.
294 *
295 *
296 ************************************************************************/
297#if defined(CONFIG_PCI)
298int is_pci_host(struct pci_controller *hose)
299{
300 /* The ocotea board is always configured as host. */
301 return(1);
302}
303#endif /* defined(CONFIG_PCI) */
304
305#ifdef CONFIG_POST
306/*
307 * Returns 1 if keys pressed to start the power-on long-running tests
308 * Called from board_init_f().
309 */
310int post_hotkeys_pressed(void)
311{
312 return (ctrlc());
313}
314#endif
Ben Warren10efa022008-08-31 20:37:00 -0700315
316int board_eth_init(bd_t *bis)
317{
Stefan Roesecef0efa2009-02-11 09:29:33 +0100318 cpu_eth_init(bis);
Ben Warren10efa022008-08-31 20:37:00 -0700319 return pci_eth_init(bis);
320}