Gitiles
Code Review Sign In
gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 35546f6f2014282cc4f9772324b5588bd44a2938 / . / arch / arm / mach-socfpga / Kconfig
blob: c4432cfe104f277e7bd460d0491b917776b7827f [file] [log] [blame]
Masahiro Yamada7865f4b2015-04-21 20:38:20 +0900[diff] [blame]1if ARCH_SOCFPGA
2
Marek Vasutcd9b7312015-08-02 21:57:57 +0200[diff] [blame]3config TARGET_SOCFPGA_ARRIA5
4 bool
Dinh Nguyened77aeb2015-12-02 13:31:25 -0600[diff] [blame]5 select TARGET_SOCFPGA_GEN5
Marek Vasutcd9b7312015-08-02 21:57:57 +0200[diff] [blame]6
7config TARGET_SOCFPGA_CYCLONE5
8 bool
Dinh Nguyened77aeb2015-12-02 13:31:25 -0600[diff] [blame]9 select TARGET_SOCFPGA_GEN5
10
11config TARGET_SOCFPGA_GEN5
12 bool
Marek Vasutcd9b7312015-08-02 21:57:57 +0200[diff] [blame]13
Masahiro Yamada7865f4b2015-04-21 20:38:20 +0900[diff] [blame]14choice
15 prompt "Altera SOCFPGA board select"
Joe Hershbergera26cd042015-05-12 14:46:23 -0500[diff] [blame]16 optional
Masahiro Yamada7865f4b2015-04-21 20:38:20 +0900[diff] [blame]17
Marek Vasutcd9b7312015-08-02 21:57:57 +0200[diff] [blame]18config TARGET_SOCFPGA_ARRIA5_SOCDK
19 bool "Altera SOCFPGA SoCDK (Arria V)"
20 select TARGET_SOCFPGA_ARRIA5
Masahiro Yamada7865f4b2015-04-21 20:38:20 +0900[diff] [blame]21
Marek Vasutcd9b7312015-08-02 21:57:57 +0200[diff] [blame]22config TARGET_SOCFPGA_CYCLONE5_SOCDK
23 bool "Altera SOCFPGA SoCDK (Cyclone V)"
24 select TARGET_SOCFPGA_CYCLONE5
Masahiro Yamada7865f4b2015-04-21 20:38:20 +0900[diff] [blame]25
Marek Vasutd88995a2015-08-03 01:37:28 +0200[diff] [blame]26config TARGET_SOCFPGA_DENX_MCVEVK
27 bool "DENX MCVEVK (Cyclone V)"
28 select TARGET_SOCFPGA_CYCLONE5
29
Stefan Roeseae9996c2015-11-18 11:06:09 +0100[diff] [blame]30config TARGET_SOCFPGA_SR1500
31 bool "SR1500 (Cyclone V)"
32 select TARGET_SOCFPGA_CYCLONE5
33
Marek Vasut856b30d2015-11-23 17:06:27 +0100[diff] [blame]34config TARGET_SOCFPGA_EBV_SOCRATES
35 bool "EBV SoCrates (Cyclone V)"
36 select TARGET_SOCFPGA_CYCLONE5
37
Pavel Machek35546f62016-06-07 12:37:23 +0200[diff] [blame^]38config TARGET_SOCFPGA_IS1
39 bool "IS1 (Cyclone V)"
40 select TARGET_SOCFPGA_CYCLONE5
41
Marek Vasut569a1912015-12-01 18:09:52 +0100[diff] [blame]42config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
43 bool "samtec VIN|ING FPGA (Cyclone V)"
44 select TARGET_SOCFPGA_CYCLONE5
45
Dinh Nguyen55c7a762015-09-01 17:41:52 -0500[diff] [blame]46config TARGET_SOCFPGA_TERASIC_DE0_NANO
47 bool "Terasic DE0-Nano-Atlas (Cyclone V)"
48 select TARGET_SOCFPGA_CYCLONE5
49
Marek Vasut952caa22015-06-21 17:28:53 +0200[diff] [blame]50config TARGET_SOCFPGA_TERASIC_SOCKIT
51 bool "Terasic SoCkit (Cyclone V)"
52 select TARGET_SOCFPGA_CYCLONE5
53
Masahiro Yamada7865f4b2015-04-21 20:38:20 +0900[diff] [blame]54endchoice
55
56config SYS_BOARD
Marek Vasutf0892402015-08-10 21:24:53 +0200[diff] [blame]57 default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
58 default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Dinh Nguyen55c7a762015-09-01 17:41:52 -0500[diff] [blame]59 default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Pavel Machek35546f62016-06-07 12:37:23 +0200[diff] [blame^]60 default "is1" if TARGET_SOCFPGA_IS1
Marek Vasutd88995a2015-08-03 01:37:28 +0200[diff] [blame]61 default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
Marek Vasut952caa22015-06-21 17:28:53 +0200[diff] [blame]62 default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut856b30d2015-11-23 17:06:27 +0100[diff] [blame]63 default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roeseae9996c2015-11-18 11:06:09 +0100[diff] [blame]64 default "sr1500" if TARGET_SOCFPGA_SR1500
Marek Vasut569a1912015-12-01 18:09:52 +0100[diff] [blame]65 default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Masahiro Yamada7865f4b2015-04-21 20:38:20 +0900[diff] [blame]66
67config SYS_VENDOR
Marek Vasutcd9b7312015-08-02 21:57:57 +0200[diff] [blame]68 default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
69 default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Marek Vasutd88995a2015-08-03 01:37:28 +0200[diff] [blame]70 default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
Marek Vasut856b30d2015-11-23 17:06:27 +0100[diff] [blame]71 default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
Marek Vasut569a1912015-12-01 18:09:52 +0100[diff] [blame]72 default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Dinh Nguyen55c7a762015-09-01 17:41:52 -0500[diff] [blame]73 default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Marek Vasut952caa22015-06-21 17:28:53 +0200[diff] [blame]74 default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
Masahiro Yamada7865f4b2015-04-21 20:38:20 +0900[diff] [blame]75
76config SYS_SOC
77 default "socfpga"
78
79config SYS_CONFIG_NAME
Dinh Nguyen3cbc7b82015-09-22 17:01:32 -0500[diff] [blame]80 default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
81 default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Dinh Nguyen55c7a762015-09-01 17:41:52 -0500[diff] [blame]82 default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Pavel Machek35546f62016-06-07 12:37:23 +0200[diff] [blame^]83 default "socfpga_is1" if TARGET_SOCFPGA_IS1
Marek Vasutd88995a2015-08-03 01:37:28 +0200[diff] [blame]84 default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
Marek Vasut952caa22015-06-21 17:28:53 +0200[diff] [blame]85 default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut856b30d2015-11-23 17:06:27 +0100[diff] [blame]86 default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roeseae9996c2015-11-18 11:06:09 +0100[diff] [blame]87 default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
Marek Vasut569a1912015-12-01 18:09:52 +0100[diff] [blame]88 default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Masahiro Yamada7865f4b2015-04-21 20:38:20 +0900[diff] [blame]89
90endif