blob: d68c48e637372bb8cf1f4ddd21f25c801c40f165 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Ajay Bhargav0c442292011-08-22 17:57:38 +05302/*
3 * (C) Copyright 2011
4 * eInfochips Ltd. <www.einfochips.com>
Ajay Bhargavc7c47ca2016-12-21 13:28:06 +05305 * Written-by: Ajay Bhargav <contact@8051projects.net>
Ajay Bhargav0c442292011-08-22 17:57:38 +05306 *
7 * (C) Copyright 2010
8 * Marvell Semiconductor <www.marvell.com>
Ajay Bhargav0c442292011-08-22 17:57:38 +05309 */
10
11#ifndef __MVGPIO_H__
12#define __MVGPIO_H__
13
14#include <common.h>
15
Ajay Bhargav0c442292011-08-22 17:57:38 +053016/*
Zhou Zhu3d046f62015-03-23 17:57:01 -050017 * GPIO Register map for Marvell SOCs
Ajay Bhargav0c442292011-08-22 17:57:38 +053018 */
19struct gpio_reg {
20 u32 gplr; /* Pin Level Register - 0x0000 */
21 u32 pad0[2];
22 u32 gpdr; /* Pin Direction Register - 0x000C */
23 u32 pad1[2];
24 u32 gpsr; /* Pin Output Set Register - 0x0018 */
25 u32 pad2[2];
26 u32 gpcr; /* Pin Output Clear Register - 0x0024 */
27 u32 pad3[2];
28 u32 grer; /* Rising-Edge Detect Enable Register - 0x0030 */
29 u32 pad4[2];
30 u32 gfer; /* Falling-Edge Detect Enable Register - 0x003C */
31 u32 pad5[2];
32 u32 gedr; /* Edge Detect Status Register - 0x0048 */
33 u32 pad6[2];
34 u32 gsdr; /* Bitwise Set of GPIO Direction Register - 0x0054 */
35 u32 pad7[2];
36 u32 gcdr; /* Bitwise Clear of GPIO Direction Register - 0x0060 */
37 u32 pad8[2];
38 u32 gsrer; /* Bitwise Set of Rising-Edge Detect Enable
39 Register - 0x006C */
40 u32 pad9[2];
41 u32 gcrer; /* Bitwise Clear of Rising-Edge Detect Enable
42 Register - 0x0078 */
43 u32 pad10[2];
44 u32 gsfer; /* Bitwise Set of Falling-Edge Detect Enable
45 Register - 0x0084 */
46 u32 pad11[2];
47 u32 gcfer; /* Bitwise Clear of Falling-Edge Detect Enable
48 Register - 0x0090 */
49 u32 pad12[2];
50 u32 apmask; /* Bitwise Mask of Edge Detect Register - 0x009C */
51};
Ajay Bhargav0c442292011-08-22 17:57:38 +053052
53#endif /* __MVGPIO_H__ */