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Aubrey.Li3f0606a2007-03-09 13:38:44 +08001/*
2 * U-boot - Configuration file for BF533 STAMP board
3 */
4
Mike Frysingercf6f4692008-06-01 09:09:48 -04005#ifndef __CONFIG_BF533_STAMP_H__
6#define __CONFIG_BF533_STAMP_H__
Aubrey.Li3f0606a2007-03-09 13:38:44 +08007
Mike Frysingerf348ab82009-04-24 17:22:40 -04008#include <asm/config-pre.h>
Mike Frysingerf7ce12c2008-02-18 05:26:48 -05009
Aubrey.Li3f0606a2007-03-09 13:38:44 +080010
Aubrey.Li3f0606a2007-03-09 13:38:44 +080011/*
Mike Frysingercf6f4692008-06-01 09:09:48 -040012 * Processor Settings
Aubrey.Li3f0606a2007-03-09 13:38:44 +080013 */
Mike Frysingerfbcf8e82010-12-23 14:58:37 -050014#define CONFIG_BFIN_CPU bf533-0.3
Mike Frysingercf6f4692008-06-01 09:09:48 -040015#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
16
Mike Frysingercf6f4692008-06-01 09:09:48 -040017/*
18 * Clock Settings
19 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
20 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
21 */
22/* CONFIG_CLKIN_HZ is any value in Hz */
23#define CONFIG_CLKIN_HZ 11059200
24/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
25/* 1 = CLKIN / 2 */
26#define CONFIG_CLKIN_HALF 0
27/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
28/* 1 = bypass PLL */
29#define CONFIG_PLL_BYPASS 0
30/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
31/* Values can range from 0-63 (where 0 means 64) */
Mike Frysinger9f64ba22008-10-12 23:49:13 -040032#define CONFIG_VCO_MULT 45
Mike Frysingercf6f4692008-06-01 09:09:48 -040033/* CCLK_DIV controls the core clock divider */
34/* Values can be 1, 2, 4, or 8 ONLY */
35#define CONFIG_CCLK_DIV 1
36/* SCLK_DIV controls the system clock divider */
37/* Values can range from 1-15 */
Mike Frysingerbaf35702009-07-10 10:42:06 -040038#define CONFIG_SCLK_DIV 6 /* note: 1.2 boards can go faster */
Mike Frysingercf6f4692008-06-01 09:09:48 -040039
Mike Frysingercf6f4692008-06-01 09:09:48 -040040/*
41 * Memory Settings
42 */
43#define CONFIG_MEM_ADD_WDTH 11
44#define CONFIG_MEM_SIZE 128
45
46#define CONFIG_EBIU_SDRRC_VAL 0x268
47#define CONFIG_EBIU_SDGCTL_VAL 0x911109
48
49#define CONFIG_EBIU_AMGCTL_VAL 0xFF
50#define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3
51#define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983
52
53#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
54#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
55
56
57/*
58 * Network Settings
59 */
60#define ADI_CMDS_NETWORK 1
Ben Warren7194ab82009-10-04 22:37:03 -070061#define CONFIG_SMC91111 1
Aubrey Li8db13d62007-03-10 23:49:29 +080062#define CONFIG_SMC91111_BASE 0x20300300
Mike Frysingercf6f4692008-06-01 09:09:48 -040063#define SMC91111_EEPROM_INIT() \
64 do { \
Ben Warren7194ab82009-10-04 22:37:03 -070065 bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); \
66 bfin_write_FIO_FLAG_C(PF1); \
67 bfin_write_FIO_FLAG_S(PF0); \
Mike Frysingercf6f4692008-06-01 09:09:48 -040068 SSYNC(); \
69 } while (0)
70#define CONFIG_HOSTNAME bf533-stamp
71/* Uncomment next line to use fixed MAC address */
72/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */
Aubrey.Li3f0606a2007-03-09 13:38:44 +080073
Aubrey.Li3f0606a2007-03-09 13:38:44 +080074
Heiko Schocherea818db2013-01-29 08:53:15 +010075/* I2C */
76#define CONFIG_SYS_I2C
77#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
78#define CONFIG_SYS_I2C_SOFT_SPEED 50000
79#define CONFIG_SYS_I2C_SOFT_SLAVE 0
80/*
81 * Software (bit-bang) I2C driver configuration
82 */
Sonic Zhange5cb60a2013-11-18 18:59:18 +080083#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF3
84#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF2
Heiko Schocherea818db2013-01-29 08:53:15 +010085
Aubrey.Li3f0606a2007-03-09 13:38:44 +080086/*
Mike Frysingercf6f4692008-06-01 09:09:48 -040087 * Flash Settings
Aubrey.Li3f0606a2007-03-09 13:38:44 +080088 */
Mike Frysingercf6f4692008-06-01 09:09:48 -040089#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#define CONFIG_SYS_FLASH_BASE 0x20000000
Mike Frysingercf6f4692008-06-01 09:09:48 -040091#define CONFIG_SYS_FLASH_CFI
92#define CONFIG_SYS_FLASH_CFI_AMD_RESET
93#define CONFIG_SYS_MAX_FLASH_BANKS 1
94#define CONFIG_SYS_MAX_FLASH_SECT 67
Aubrey.Li3f0606a2007-03-09 13:38:44 +080095
Mike Frysingercf6f4692008-06-01 09:09:48 -040096/*
97 * SPI Settings
98 */
99#define CONFIG_BFIN_SPI
100#define CONFIG_ENV_SPI_MAX_HZ 30000000
Mike Frysingerafac8b02009-06-14 22:29:35 -0400101#define CONFIG_SF_DEFAULT_SPEED 30000000
Mike Frysingercf6f4692008-06-01 09:09:48 -0400102#define CONFIG_SPI_FLASH
Mike Frysingerf4532202010-09-19 16:26:55 -0400103#define CONFIG_SPI_FLASH_ALL
Mike Frysingercf6f4692008-06-01 09:09:48 -0400104
105
106/*
107 * Env Storage Settings
108 */
Mike Frysinger9171fc82008-03-30 15:46:13 -0400109#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
Mike Frysingercf6f4692008-06-01 09:09:48 -0400110#define CONFIG_ENV_IS_IN_SPI_FLASH
Vivi Libc43a8d2009-06-12 10:53:22 +0000111#define CONFIG_ENV_OFFSET 0x10000
Mike Frysingercf6f4692008-06-01 09:09:48 -0400112#define CONFIG_ENV_SIZE 0x2000
Vivi Libc43a8d2009-06-12 10:53:22 +0000113#define CONFIG_ENV_SECT_SIZE 0x10000
Mike Frysinger9171fc82008-03-30 15:46:13 -0400114#else
Mike Frysingercf6f4692008-06-01 09:09:48 -0400115#define CONFIG_ENV_IS_IN_FLASH
116#define CONFIG_ENV_OFFSET 0x4000
117#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
118#define CONFIG_ENV_SIZE 0x2000
119#define CONFIG_ENV_SECT_SIZE 0x2000
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800120#endif
Mike Frysingercf6f4692008-06-01 09:09:48 -0400121#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
122#define ENV_IS_EMBEDDED
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800123#else
Mike Frysinger76d82182009-07-21 22:17:36 -0400124#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800125#endif
Mike Frysinger9ff67e52009-06-14 06:29:07 -0400126#ifdef ENV_IS_EMBEDDED
127/* WARNING - the following is hand-optimized to fit within
128 * the sector before the environment sector. If it throws
129 * an error during compilation remove an object here to get
130 * it linked after the configuration sector.
131 */
132# define LDS_BOARD_TEXT \
Masahiro Yamadae2906a52013-11-11 14:36:00 +0900133 arch/blackfin/lib/built-in.o (.text*); \
134 arch/blackfin/cpu/built-in.o (.text*); \
Mike Frysinger9ff67e52009-06-14 06:29:07 -0400135 . = DEFINED(env_offset) ? env_offset : .; \
Mike Frysingerc70e7dd2010-11-19 19:28:56 -0500136 common/env_embedded.o (.text*);
Mike Frysinger9ff67e52009-06-14 06:29:07 -0400137#endif
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800138
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800139
Jon Loeligerba2351f2007-07-04 22:31:49 -0500140/*
Mike Frysingercf6f4692008-06-01 09:09:48 -0400141 * I2C Settings
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800142 */
Heiko Schocherea818db2013-01-29 08:53:15 +0100143#define CONFIG_SYS_I2C_SOFT
144#ifdef CONFIG_SYS_I2C_SOFT
145#define CONFIG_SYS_I2C
Mike Frysingerbeb60e72010-06-08 16:22:44 -0400146#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF3
147#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF2
Heiko Schocherea818db2013-01-29 08:53:15 +0100148#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
149#define CONFIG_SYS_I2C_SOFT_SPEED 50000
150#define CONFIG_SYS_I2C_SOFT_SLAVE 0
151#endif
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800152
153/*
Mike Frysingercf6f4692008-06-01 09:09:48 -0400154 * Compact Flash / IDE / ATA Settings
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800155 */
156
157/* Enabled below option for CF support */
Mike Frysingercf6f4692008-06-01 09:09:48 -0400158/* #define CONFIG_STAMP_CF */
159#if defined(CONFIG_STAMP_CF)
160#define CONFIG_MISC_INIT_R
Aubrey Li8db13d62007-03-10 23:49:29 +0800161#define CONFIG_DOS_PARTITION 1
Aubrey Li8db13d62007-03-10 23:49:29 +0800162#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
163#undef CONFIG_IDE_LED /* no led for ide supported */
164#undef CONFIG_IDE_RESET /* no reset for ide supported */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800165
Mike Frysingercf6f4692008-06-01 09:09:48 -0400166#define CONFIG_SYS_IDE_MAXBUS 1
167#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1)
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800168
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_ATA_BASE_ADDR 0x20200000
170#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800171
Mike Frysingercf6f4692008-06-01 09:09:48 -0400172#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */
173#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */
174#define CONFIG_SYS_ATA_ALT_OFFSET 0x0007 /* alternate registers */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800175
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_ATA_STRIDE 2
Mike Frysingercf6f4692008-06-01 09:09:48 -0400177
178#undef CONFIG_EBIU_AMBCTL1_VAL
179#define CONFIG_EBIU_AMBCTL1_VAL 0x99B3ffc2
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800180#endif
181
Mike Frysingercf6f4692008-06-01 09:09:48 -0400182
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800183/*
Mike Frysingercf6f4692008-06-01 09:09:48 -0400184 * Misc Settings
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800185 */
Mike Frysingercf6f4692008-06-01 09:09:48 -0400186#define CONFIG_RTC_BFIN
187#define CONFIG_UART_CONSOLE 0
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800188
Mike Frysingercf6f4692008-06-01 09:09:48 -0400189/* FLASH/ETHERNET uses the same async bank */
190#define SHARED_RESOURCES 1
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800191
Mike Frysinger23fd9592008-10-11 22:40:22 -0400192/* define to enable boot progress via leds */
193/* #define CONFIG_SHOW_BOOT_PROGRESS */
194
195/* define to enable run status via led */
196/* #define CONFIG_STATUS_LED */
197#ifdef CONFIG_STATUS_LED
Mike Frysingera84774f2010-06-02 05:12:11 -0400198#define CONFIG_GPIO_LED
Mike Frysinger23fd9592008-10-11 22:40:22 -0400199#define CONFIG_BOARD_SPECIFIC_LED
Mike Frysingera84774f2010-06-02 05:12:11 -0400200/* use LED0 to indicate booting/alive */
Mike Frysinger23fd9592008-10-11 22:40:22 -0400201#define STATUS_LED_BOOT 0
Mike Frysingera84774f2010-06-02 05:12:11 -0400202#define STATUS_LED_BIT GPIO_PF2
Mike Frysinger23fd9592008-10-11 22:40:22 -0400203#define STATUS_LED_STATE STATUS_LED_ON
204#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 4)
Mike Frysingera84774f2010-06-02 05:12:11 -0400205/* use LED1 to indicate crash */
Mike Frysinger23fd9592008-10-11 22:40:22 -0400206#define STATUS_LED_CRASH 1
Mike Frysingera84774f2010-06-02 05:12:11 -0400207#define STATUS_LED_BIT1 GPIO_PF3
Mike Frysinger23fd9592008-10-11 22:40:22 -0400208#define STATUS_LED_STATE1 STATUS_LED_ON
209#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
Mike Frysingera84774f2010-06-02 05:12:11 -0400210/* #define STATUS_LED_BIT2 GPIO_PF4 */
Mike Frysinger23fd9592008-10-11 22:40:22 -0400211#endif
212
Mike Frysingercf6f4692008-06-01 09:09:48 -0400213/* define to enable splash screen support */
214/* #define CONFIG_VIDEO */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800215
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800216
217/*
Mike Frysingercf6f4692008-06-01 09:09:48 -0400218 * Pull in common ADI header for remaining command/environment setup
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800219 */
Mike Frysingercf6f4692008-06-01 09:09:48 -0400220#include <configs/bfin_adi_common.h>
Mike Frysinger9171fc82008-03-30 15:46:13 -0400221
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800222#endif