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Vasily Khoruzhick1c353ae2018-05-14 08:16:20 -07001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (c) 2017-2018 Vasily Khoruzhick <anarsoul@gmail.com>
4 */
5
6#include <common.h>
7#include <div64.h>
8#include <dm.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -06009#include <log.h>
Vasily Khoruzhick1c353ae2018-05-14 08:16:20 -070010#include <pwm.h>
11#include <regmap.h>
12#include <syscon.h>
13#include <asm/io.h>
14#include <asm/arch/pwm.h>
15#include <asm/arch/gpio.h>
16#include <power/regulator.h>
17
18DECLARE_GLOBAL_DATA_PTR;
19
20#define OSC_24MHZ 24000000
21
22struct sunxi_pwm_priv {
23 struct sunxi_pwm *regs;
24 bool invert;
25 u32 prescaler;
26};
27
28static const u32 prescaler_table[] = {
29 120, /* 0000 */
30 180, /* 0001 */
31 240, /* 0010 */
32 360, /* 0011 */
33 480, /* 0100 */
34 0, /* 0101 */
35 0, /* 0110 */
36 0, /* 0111 */
37 12000, /* 1000 */
38 24000, /* 1001 */
39 36000, /* 1010 */
40 48000, /* 1011 */
41 72000, /* 1100 */
42 0, /* 1101 */
43 0, /* 1110 */
44 1, /* 1111 */
45};
46
47static int sunxi_pwm_config_pinmux(void)
48{
49#ifdef CONFIG_MACH_SUN50I
50 sunxi_gpio_set_cfgpin(SUNXI_GPD(22), SUNXI_GPD_PWM);
51#endif
52 return 0;
53}
54
55static int sunxi_pwm_set_invert(struct udevice *dev, uint channel,
56 bool polarity)
57{
58 struct sunxi_pwm_priv *priv = dev_get_priv(dev);
59
60 debug("%s: polarity=%u\n", __func__, polarity);
61 priv->invert = polarity;
62
63 return 0;
64}
65
66static int sunxi_pwm_set_config(struct udevice *dev, uint channel,
67 uint period_ns, uint duty_ns)
68{
69 struct sunxi_pwm_priv *priv = dev_get_priv(dev);
70 struct sunxi_pwm *regs = priv->regs;
Vasily Khoruzhickc33ba7e2018-10-16 21:56:35 -070071 int best_prescaler = 0;
72 u32 v, best_period = 0, duty;
73 u64 best_scaled_freq = 0;
Vasily Khoruzhick1c353ae2018-05-14 08:16:20 -070074 const u32 nsecs_per_sec = 1000000000U;
75
76 debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns);
77
Vasily Khoruzhickc33ba7e2018-10-16 21:56:35 -070078 for (int prescaler = 0; prescaler <= SUNXI_PWM_CTRL_PRESCALE0_MASK;
Vasily Khoruzhick1c353ae2018-05-14 08:16:20 -070079 prescaler++) {
Vasily Khoruzhickc33ba7e2018-10-16 21:56:35 -070080 u32 period = 0;
81 u64 scaled_freq = 0;
Vasily Khoruzhick1c353ae2018-05-14 08:16:20 -070082 if (!prescaler_table[prescaler])
83 continue;
84 scaled_freq = lldiv(OSC_24MHZ, prescaler_table[prescaler]);
85 period = lldiv(scaled_freq * period_ns, nsecs_per_sec);
Vasily Khoruzhickc33ba7e2018-10-16 21:56:35 -070086 if ((period - 1 <= SUNXI_PWM_CH0_PERIOD_MAX) &&
87 best_period < period) {
88 best_period = period;
89 best_scaled_freq = scaled_freq;
90 best_prescaler = prescaler;
91 }
Vasily Khoruzhick1c353ae2018-05-14 08:16:20 -070092 }
93
Vasily Khoruzhickc33ba7e2018-10-16 21:56:35 -070094 if (best_period - 1 > SUNXI_PWM_CH0_PERIOD_MAX) {
Vasily Khoruzhick1c353ae2018-05-14 08:16:20 -070095 debug("%s: failed to find prescaler value\n", __func__);
96 return -EINVAL;
97 }
98
Vasily Khoruzhickc33ba7e2018-10-16 21:56:35 -070099 duty = lldiv(best_scaled_freq * duty_ns, nsecs_per_sec);
Vasily Khoruzhick1c353ae2018-05-14 08:16:20 -0700100
Vasily Khoruzhickc33ba7e2018-10-16 21:56:35 -0700101 if (priv->prescaler != best_prescaler) {
Vasily Khoruzhick1c353ae2018-05-14 08:16:20 -0700102 /* Mask clock to update prescaler */
103 v = readl(&regs->ctrl);
104 v &= ~SUNXI_PWM_CTRL_CLK_GATE;
105 writel(v, &regs->ctrl);
106 v &= ~SUNXI_PWM_CTRL_PRESCALE0_MASK;
Vasily Khoruzhickc33ba7e2018-10-16 21:56:35 -0700107 v |= (best_prescaler & SUNXI_PWM_CTRL_PRESCALE0_MASK);
Vasily Khoruzhick1c353ae2018-05-14 08:16:20 -0700108 writel(v, &regs->ctrl);
109 v |= SUNXI_PWM_CTRL_CLK_GATE;
110 writel(v, &regs->ctrl);
Vasily Khoruzhickc33ba7e2018-10-16 21:56:35 -0700111 priv->prescaler = best_prescaler;
Vasily Khoruzhick1c353ae2018-05-14 08:16:20 -0700112 }
113
Vasily Khoruzhickc33ba7e2018-10-16 21:56:35 -0700114 writel(SUNXI_PWM_CH0_PERIOD_PRD(best_period) |
Vasily Khoruzhick1c353ae2018-05-14 08:16:20 -0700115 SUNXI_PWM_CH0_PERIOD_DUTY(duty), &regs->ch0_period);
116
117 debug("%s: prescaler: %d, period: %d, duty: %d\n",
118 __func__, priv->prescaler,
Vasily Khoruzhickc33ba7e2018-10-16 21:56:35 -0700119 best_period, duty);
Vasily Khoruzhick1c353ae2018-05-14 08:16:20 -0700120
121 return 0;
122}
123
124static int sunxi_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
125{
126 struct sunxi_pwm_priv *priv = dev_get_priv(dev);
127 struct sunxi_pwm *regs = priv->regs;
128 u32 v;
129
130 debug("%s: Enable '%s'\n", __func__, dev->name);
131
132 v = readl(&regs->ctrl);
133 if (!enable) {
134 v &= ~SUNXI_PWM_CTRL_ENABLE0;
135 writel(v, &regs->ctrl);
136 return 0;
137 }
138
139 sunxi_pwm_config_pinmux();
140
141 if (priv->invert)
142 v &= ~SUNXI_PWM_CTRL_CH0_ACT_STA;
143 else
144 v |= SUNXI_PWM_CTRL_CH0_ACT_STA;
145 v |= SUNXI_PWM_CTRL_ENABLE0;
146 writel(v, &regs->ctrl);
147
148 return 0;
149}
150
151static int sunxi_pwm_ofdata_to_platdata(struct udevice *dev)
152{
153 struct sunxi_pwm_priv *priv = dev_get_priv(dev);
154
Masahiro Yamada8613c8d2020-07-17 14:36:46 +0900155 priv->regs = dev_read_addr_ptr(dev);
Vasily Khoruzhick1c353ae2018-05-14 08:16:20 -0700156
157 return 0;
158}
159
160static int sunxi_pwm_probe(struct udevice *dev)
161{
162 return 0;
163}
164
165static const struct pwm_ops sunxi_pwm_ops = {
166 .set_invert = sunxi_pwm_set_invert,
167 .set_config = sunxi_pwm_set_config,
168 .set_enable = sunxi_pwm_set_enable,
169};
170
171static const struct udevice_id sunxi_pwm_ids[] = {
172 { .compatible = "allwinner,sun5i-a13-pwm" },
173 { .compatible = "allwinner,sun50i-a64-pwm" },
174 { }
175};
176
177U_BOOT_DRIVER(sunxi_pwm) = {
178 .name = "sunxi_pwm",
179 .id = UCLASS_PWM,
180 .of_match = sunxi_pwm_ids,
181 .ops = &sunxi_pwm_ops,
182 .ofdata_to_platdata = sunxi_pwm_ofdata_to_platdata,
183 .probe = sunxi_pwm_probe,
184 .priv_auto_alloc_size = sizeof(struct sunxi_pwm_priv),
185};