blob: 011aed08417ad008d4f48cebc5a577b8d47f2176 [file] [log] [blame]
Helmut Raiger4d86dd02011-10-27 01:31:15 +00001/*
2 * (C) Copyright 2011 HALE electronic <helmut.raiger@hale.at>
3 * (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
4 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Helmut Raiger4d86dd02011-10-27 01:31:15 +00007 */
8
9#include <common.h>
10#include <netdev.h>
11#include <command.h>
Łukasz Majewskic7336812012-11-13 03:21:55 +000012#include <power/pmic.h>
Helmut Raigerf3535182012-01-18 21:27:13 +000013#include <fsl_pmic.h>
14#include <mc13783.h>
Helmut Raiger4d86dd02011-10-27 01:31:15 +000015#include <asm/arch/clock.h>
16#include <asm/arch/sys_proto.h>
17#include <asm/io.h>
Łukasz Majewskic7336812012-11-13 03:21:55 +000018#include <errno.h>
Helmut Raiger4d86dd02011-10-27 01:31:15 +000019
20DECLARE_GLOBAL_DATA_PTR;
21
22#define BOARD_STRING "Board: HALE TT-01"
23
24/* Clock configuration */
25#define CCM_CCMR_SETUP 0x074B0BF5
26
27static void board_setup_clocks(void)
28{
29 struct clock_control_regs *ccm = (struct clock_control_regs *) CCM_BASE;
30 volatile int wait = 0x10000;
31
32 writel(CCM_CCMR_SETUP, &ccm->ccmr);
33 while (wait--)
34 ;
35
36 writel(CCM_CCMR_SETUP | CCMR_MPE, &ccm->ccmr);
37 writel((CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS, &ccm->ccmr);
38
39 /* Set up clock to 532MHz */
Benoît Thébaudeau9e0081d2012-08-14 08:43:07 +000040 writel(PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) |
Helmut Raiger4d86dd02011-10-27 01:31:15 +000041 PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) |
42 PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) |
43 PDR0_MCU_PODF(0), &ccm->pdr0);
44 writel(PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | PLL_MFN(12),
45 &ccm->mpctl);
46 writel(PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1),
47 &ccm->spctl);
48}
49
50/* DRAM configuration */
51
52#define ESDMISC_MDDR_SETUP 0x00000004
53#define ESDMISC_MDDR_RESET_DL 0x0000000c
54/*
55 * decoding magic 0x6ac73a = 0b 0110 1010 1100 0111 0011 1010 below:
56 * tXP = 11, tWTR = 0, tRP = 10, tMRD = 10
57 * tWR = 1, tRAS = 100, tRRD = 01, tCAS = 11
58 * tRCD = 011, tRC = 010
59 * note: all but tWTR (1), tRC (111) are reset defaults,
60 * the same values work in the jtag configuration
61 *
62 * Bluetechnix setup has 0x75e73a (for 128MB) =
63 * 0b 0111 0101 1110 0111 0011 1010
64 * tXP = 11, tWTR = 1, tRP = 01, tMRD = 01
65 * tWR = 1, tRAS = 110, tRRD = 01, tCAS = 11
66 * tRCD = 011, tRC = 010
67 */
68#define ESDCFG0_MDDR_SETUP 0x006ac73a
69#define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2))
70#define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \
71 ESDCTL_DSIZ(2) | ESDCTL_BL(1))
72#define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE)
73#define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH)
74#define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG)
75#define ESDCTL_RW ESDCTL_SETTINGS
76
77static void board_setup_sdram(void)
78{
79 u32 *pad;
80 struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
81
82 /*
83 * setup pad control for the controller pins
84 * no loopback, no pull, no keeper, no open drain,
85 * standard input, standard drive, slow slew rate
86 */
87 for (pad = (u32 *) IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B;
88 pad <= (u32 *) IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0; pad++)
89 *pad = 0;
90
91 /* set up MX31 DDR Memory Controller */
92 writel(ESDMISC_MDDR_SETUP, &esdc->misc);
93 writel(ESDCFG0_MDDR_SETUP, &esdc->cfg0);
94
95 /* perform DDR init sequence for CSD0 */
96 writel(ESDCTL_PRECHARGE, &esdc->ctl0);
97 writel(0x12344321, CSD0_BASE+0x0f00);
98 writel(ESDCTL_AUTOREFRESH, &esdc->ctl0);
99 writel(0x12344321, CSD0_BASE);
100 writel(0x12344321, CSD0_BASE);
101 writel(ESDCTL_LOADMODEREG, &esdc->ctl0);
102 writeb(0xda, CSD0_BASE+0x33);
103 writeb(0xff, CSD0_BASE+0x1000000);
104 writel(ESDCTL_RW, &esdc->ctl0);
105 writel(0xDEADBEEF, CSD0_BASE);
106 writel(ESDMISC_MDDR_RESET_DL, &esdc->misc);
107}
108
109static void tt01_spi3_hw_init(void)
110{
111 /* CSPI3 */
112 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_MISO, MUX_CTL_FUNC));
113 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_MOSI, MUX_CTL_FUNC));
114 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI3_SCLK, MUX_CTL_FUNC));
115 /* CSPI3, SS0 = Atlas */
116 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CSPI2_SS0, MUX_CTL_ALT1));
117
118 /* start CSPI3 clock (3 = always on except if PLL off) */
119 setbits_le32(CCM_CGR0, 3 << 16);
120}
121
122int dram_init(void)
123{
124 /* dram_init must store complete ramsize in gd->ram_size */
125 gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE,
126 PHYS_SDRAM_1_SIZE);
127 return 0;
128}
129
130int board_early_init_f(void)
131{
132 /* CS4: FPGA incl. network controller */
133 struct mxc_weimcs cs4 = {
134 /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
135 CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 28, 1, 7, 6),
136 /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
137 CSCR_L(4, 4, 4, 10, 4, 0, 5, 4, 0, 0, 0, 1),
138 /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
139 CSCR_A(4, 4, 4, 4, 0, 1, 4, 3, 0, 0, 0, 0, 1, 0)
140 };
141
142 /* this seems essential, won't start without, but why? */
143 writel(IPU_CONF_DI_EN, (u32 *) IPU_CONF);
144
145 board_setup_clocks();
146 board_setup_sdram();
147 mxc_setup_weimcs(4, &cs4);
148
149 /* Setup UART2 and SPI3 pins */
150 mx31_uart2_hw_init();
151 tt01_spi3_hw_init();
152
153 return 0;
154}
155
156int board_init(void)
157{
158 /* address of boot parameters */
159 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
160 return 0;
161}
162
163int board_late_init(void)
164{
Helmut Raiger4d86dd02011-10-27 01:31:15 +0000165#ifdef CONFIG_HW_WATCHDOG
Troy Kiskyabbab702012-10-22 15:19:01 +0000166 hw_watchdog_init();
Helmut Raiger4d86dd02011-10-27 01:31:15 +0000167#endif
168
169 return 0;
170}
171
172int checkboard(void)
173{
174 puts(BOARD_STRING "\n");
175 return 0;
176}
177
Helmut Raigerf3535182012-01-18 21:27:13 +0000178#ifdef CONFIG_MXC_MMC
179int board_mmc_init(bd_t *bis)
180{
181 u32 val;
182 struct pmic *p;
Łukasz Majewskic7336812012-11-13 03:21:55 +0000183 int ret;
Helmut Raigerf3535182012-01-18 21:27:13 +0000184
185 /*
186 * this is the first driver to use the pmic, so call
187 * pmic_init() here. board_late_init() is too late for
188 * the MMC driver.
189 */
Łukasz Majewskic7336812012-11-13 03:21:55 +0000190
191 ret = pmic_init(I2C_PMIC);
192 if (ret)
193 return ret;
194
195 p = pmic_get("FSL_PMIC");
196 if (!p)
197 return -ENODEV;
Helmut Raigerf3535182012-01-18 21:27:13 +0000198
199 /* configure pins for SDHC1 only */
200 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_CLK, MUX_CTL_FUNC));
201 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_CMD, MUX_CTL_FUNC));
202 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA0, MUX_CTL_FUNC));
203 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA1, MUX_CTL_FUNC));
204 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA2, MUX_CTL_FUNC));
205 mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_DATA3, MUX_CTL_FUNC));
206
207 /* turn on power V_MMC1 */
208 if (pmic_reg_read(p, REG_MODE_1, &val) < 0)
209 pmic_reg_write(p, REG_MODE_1, val | VMMC1EN);
210
211 return mxc_mmc_init(bis);
212}
213#endif
214
Helmut Raiger4d86dd02011-10-27 01:31:15 +0000215int board_eth_init(bd_t *bis)
216{
217 int rc = 0;
218#ifdef CONFIG_SMC911X
219 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
220#endif
221 return rc;
222}
Helmut Raigerd1300f72012-02-15 22:40:12 +0000223
224#ifdef CONFIG_CONSOLE_EXTRA_INFO
225void video_get_info_str(int line_number, char *info)
226{
227 u32 srev = get_cpu_rev();
228
229 switch (line_number) {
230 case 2:
231 sprintf(info, " CPU : Freescale i.MX31 rev %d.%d%s at %d MHz",
232 (srev & 0xF0) >> 4, (srev & 0x0F),
233 ((srev & 0x8000) ? " unknown" : ""),
234 mxc_get_clock(MXC_ARM_CLK) / 1000000);
235 break;
236 case 3:
237 strcpy(info, " " BOARD_STRING);
238 break;
239 default:
240 info[0] = 0;
241 }
242}
243#endif