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wdenk507bbe32004-04-18 21:13:41 +00001/*
Michal Simekcfc67112007-03-11 13:48:24 +01002 * (C) Copyright 2007 Michal Simek
wdenk507bbe32004-04-18 21:13:41 +00003 * (C) Copyright 2004 Atmark Techno, Inc.
4 *
Michal Simekcfc67112007-03-11 13:48:24 +01005 * Michal SIMEK <monstr@monstr.eu>
wdenk507bbe32004-04-18 21:13:41 +00006 * Yasushi SHOJI <yashi@atmark-techno.com>
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Michal Simekcfc67112007-03-11 13:48:24 +010018 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenk507bbe32004-04-18 21:13:41 +000019 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <config.h>
28
29 .text
30 .global _start
31_start:
Michal Simekcfc67112007-03-11 13:48:24 +010032 mts rmsr, r0 /* disable cache */
33 addi r1, r0, CFG_INIT_SP_OFFSET
34 /* add opcode instruction for 32bit jump - 2 instruction imm & brai*/
35 addi r6, r0, 0xb000 /* hex b000 opcode imm */
36 bslli r6, r6, 16 /* shift */
37 swi r6, r0, 0x0 /* reset address */
38 swi r6, r0, 0x8 /* user vector exception */
39 swi r6, r0, 0x10 /* interrupt */
40 swi r6, r0, 0x20 /* hardware exception */
wdenk507bbe32004-04-18 21:13:41 +000041
Michal Simekcfc67112007-03-11 13:48:24 +010042 addi r6, r0, 0xb808 /* hew b808 opcode brai*/
43 bslli r6, r6, 16
44 swi r6, r0, 0x4 /* reset address */
45 swi r6, r0, 0xC /* user vector exception */
46 swi r6, r0, 0x14 /* interrupt */
47 swi r6, r0, 0x24 /* hardware exception */
wdenk507bbe32004-04-18 21:13:41 +000048
Michal Simekcfc67112007-03-11 13:48:24 +010049#ifdef CFG_RESET_ADDRESS
50 /* reset address */
51 addik r6, r0, CFG_RESET_ADDRESS
52 sw r6, r1, r0
53 lhu r7, r1, r0
54 shi r7, r0, 0x2
55 shi r6, r0, 0x6
56#endif
57
58#ifdef CFG_USR_EXCEP
59 /* user_vector_exception */
60 addik r6, r0, _exception_handler
61 sw r6, r1, r0
62 lhu r7, r1, r0
63 shi r7, r0, 0xa
64 shi r6, r0, 0xe
65#endif
66
67#ifdef CFG_INTC_0
68 /* interrupt_handler */
69 addik r6, r0, _interrupt_handler
70 sw r6, r1, r0
71 lhu r7, r1, r0
72 shi r7, r0, 0x12
73 shi r6, r0, 0x16
74#endif
75
76 /* hardware exception */
77 addik r6, r0, _hw_exception_handler
78 sw r6, r1, r0
79 lhu r7, r1, r0
80 shi r7, r0, 0x22
81 shi r6, r0, 0x26
82
83 /* enable instruction and data cache */
84 mfs r12, rmsr
85 ori r12, r12, 0xa0
86 mts rmsr, r12
87
88 /* jumping to board_init */
wdenk507bbe32004-04-18 21:13:41 +000089 brai board_init
wdenk507bbe32004-04-18 21:13:41 +0000901: bri 1b