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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / cff009ed6ff7da2e87f8213d34ed869be4373604 / . / include / configs / lwmon5.h
blob: 66d9710d3362c20b2b57bca332bbbc26d956ac14 [file] [log] [blame]
Stefan Roese04386f62015-10-02 08:20:35 +0200[diff] [blame]1/*
2 * (C) Copyright 2007-2013
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8/*
9 * lwmon5.h - configuration for lwmon5 board
10 */
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14/*
15 * Liebherr extra version info
16 */
17#define CONFIG_IDENT_STRING " - v2.0"
18
19/*
20 * High Level Configuration Options
21 */
22#define CONFIG_LWMON5 1 /* Board is lwmon5 */
23#define CONFIG_440EPX 1 /* Specific PPC440EPx */
24#define CONFIG_440 1 /* ... PPC440 family */
25
Stefan Roesec0c7a552015-10-02 08:20:36 +0200[diff] [blame]26
Stefan Roese04386f62015-10-02 08:20:35 +0200[diff] [blame]27#define CONFIG_SYS_TEXT_BASE 0xFFF80000
28#define CONFIG_HOSTNAME lwmon5
Stefan Roese04386f62015-10-02 08:20:35 +0200[diff] [blame]29
30#define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */
31
32#define CONFIG_4xx_DCACHE /* enable cache in SDRAM */
33
34#define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */
35#define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */
36#define CONFIG_BOARD_POSTCLK_INIT /* Call board_postclk_init */
37#define CONFIG_MISC_INIT_R /* Call misc_init_r */
38#define CONFIG_BOARD_RESET /* Call board_reset */
39
40/*
41 * Base addresses -- Note these are effective addresses where the
42 * actual resources get mapped (not physical addresses)
43 */
44#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of U-Boot */
45#define CONFIG_SYS_MONITOR_LEN 0x80000
46#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* Reserved for malloc */
47
48#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
49#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
50#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
51#define CONFIG_SYS_LIME_BASE_0 0xc0000000
52#define CONFIG_SYS_LIME_BASE_1 0xc1000000
53#define CONFIG_SYS_LIME_BASE_2 0xc2000000
54#define CONFIG_SYS_LIME_BASE_3 0xc3000000
55#define CONFIG_SYS_FPGA_BASE_0 0xc4000000
56#define CONFIG_SYS_FPGA_BASE_1 0xc4200000
57#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
58#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
59#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
60#define CONFIG_SYS_PCI_MEMBASE1 (CONFIG_SYS_PCI_MEMBASE + 0x10000000)
61#define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE1 + 0x10000000)
62#define CONFIG_SYS_PCI_MEMBASE3 (CONFIG_SYS_PCI_MEMBASE2 + 0x10000000)
63
Stefan Roese04386f62015-10-02 08:20:35 +0200[diff] [blame]64#define CONFIG_SYS_USB2D0_BASE 0xe0000100
65#define CONFIG_SYS_USB_DEVICE 0xe0000000
66#define CONFIG_SYS_USB_HOST 0xe0000400
Stefan Roese04386f62015-10-02 08:20:35 +0200[diff] [blame]67
68/*
69 * Initial RAM & stack pointer
70 *
71 * On LWMON5 we use D-cache as init-ram and stack pointer. We also move
72 * the POST_WORD from OCM to a 440EPx register that preserves it's
73 * content during reset (GPT0_COMP6). This way we reserve the OCM (16k)
74 * for logbuffer only. (GPT0_COMP1-COMP5 are reserved for logbuffer header.)
75 */
Stefan Roese04386f62015-10-02 08:20:35 +0200[diff] [blame]76#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */
77#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
78#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
79#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
80 GENERATED_GBL_DATA_SIZE)
81#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Stefan Roeseb6b5e392015-10-02 08:20:37 +0200[diff] [blame]82
Stefan Roese04386f62015-10-02 08:20:35 +0200[diff] [blame]83/* unused GPT0 COMP reg */
84#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
85#define CONFIG_SYS_OCM_SIZE (16 << 10)
86/* 440EPx errata CHIP 11: don't use last 4kbytes */
87#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10)
88
89/* Additional registers for watchdog timer post test */
90#define CONFIG_SYS_WATCHDOG_TIME_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK2)
91#define CONFIG_SYS_WATCHDOG_FLAGS_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK1)
92#define CONFIG_SYS_DSPIC_TEST_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR
93#define CONFIG_SYS_OCM_STATUS_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR
94#define CONFIG_SYS_WATCHDOG_MAGIC 0x12480000
95#define CONFIG_SYS_WATCHDOG_MAGIC_MASK 0xFFFF0000
96#define CONFIG_SYS_DSPIC_TEST_MASK 0x00000001
97#define CONFIG_SYS_OCM_STATUS_OK 0x00009A00
98#define CONFIG_SYS_OCM_STATUS_FAIL 0x0000A300
99#define CONFIG_SYS_OCM_STATUS_MASK 0x0000FF00
100
101/*
102 * Serial Port
103 */
104#define CONFIG_CONS_INDEX 2 /* Use UART1 */
105#define CONFIG_SYS_NS16550
106#define CONFIG_SYS_NS16550_SERIAL
107#define CONFIG_SYS_NS16550_REG_SIZE 1
108#define CONFIG_SYS_NS16550_CLK get_serial_clock()
109#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clock provided */
110#define CONFIG_BAUDRATE 115200
111
112#define CONFIG_SYS_BAUDRATE_TABLE \
113 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
114
115/*
116 * Environment
117 */
118#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
119
120/*
121 * FLASH related
122 */
123#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
124#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
125
126#define CONFIG_SYS_FLASH0 0xFC000000
127#define CONFIG_SYS_FLASH1 0xF8000000
128#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
129
130#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 /* max number of memory banks */
131#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
132
133#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
134#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
135
136#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
137#define CONFIG_SYS_FLASH_PROTECTION /* use hardware flash protection */
138
139#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
140#define CONFIG_SYS_FLASH_QUIET_TEST /* don't warn upon unknown flash */
141
142#define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
143#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SECT_SIZE)
144#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
145
146/* Address and size of Redundant Environment Sector */
147#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
148#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
149
150/*
151 * DDR SDRAM
152 */
153#define CONFIG_SYS_MBYTES_SDRAM 256
154#define CONFIG_SYS_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
155#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
Stefan Roese04386f62015-10-02 08:20:35 +0200[diff] [blame]156#define CONFIG_DDR_ECC /* enable ECC */
Stefan Roese04386f62015-10-02 08:20:35 +0200[diff] [blame]157
Stefan Roese04386f62015-10-02 08:20:35 +0200[diff] [blame]158/* POST support */
159#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
160 CONFIG_SYS_POST_CPU | \
161 CONFIG_SYS_POST_ECC | \
162 CONFIG_SYS_POST_ETHER | \
163 CONFIG_SYS_POST_FPU | \
164 CONFIG_SYS_POST_I2C | \
165 CONFIG_SYS_POST_MEMORY | \
166 CONFIG_SYS_POST_OCM | \
167 CONFIG_SYS_POST_RTC | \
168 CONFIG_SYS_POST_SPR | \
169 CONFIG_SYS_POST_UART | \
170 CONFIG_SYS_POST_SYSMON | \
171 CONFIG_SYS_POST_WATCHDOG | \
172 CONFIG_SYS_POST_DSP | \
173 CONFIG_SYS_POST_BSPEC1 | \
174 CONFIG_SYS_POST_BSPEC2 | \
175 CONFIG_SYS_POST_BSPEC3 | \
176 CONFIG_SYS_POST_BSPEC4 | \
177 CONFIG_SYS_POST_BSPEC5)
178
179/* Define here the base-addresses of the UARTs to test in POST */
180#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \
181 CONFIG_SYS_NS16550_COM2 }
182
183#define CONFIG_POST_UART { \
184 "UART test", \
185 "uart", \
186 "This test verifies the UART operation.", \
187 POST_RAM | POST_SLOWTEST | POST_ALWAYS | POST_MANUAL, \
188 &uart_post_test, \
189 NULL, \
190 NULL, \
191 CONFIG_SYS_POST_UART \
192 }
193
194#define CONFIG_POST_WATCHDOG { \
195 "Watchdog timer test", \
196 "watchdog", \
197 "This test checks the watchdog timer.", \
198 POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT, \
199 &lwmon5_watchdog_post_test, \
200 NULL, \
201 NULL, \
202 CONFIG_SYS_POST_WATCHDOG \
203 }
204
205#define CONFIG_POST_BSPEC1 { \
206 "dsPIC init test", \
207 "dspic_init", \
208 "This test returns result of dsPIC READY test run earlier.", \
209 POST_RAM | POST_ALWAYS, \
210 &dspic_init_post_test, \
211 NULL, \
212 NULL, \
213 CONFIG_SYS_POST_BSPEC1 \
214 }
215
216#define CONFIG_POST_BSPEC2 { \
217 "dsPIC test", \
218 "dspic", \
219 "This test gets result of dsPIC POST and dsPIC version.", \
220 POST_RAM | POST_ALWAYS, \
221 &dspic_post_test, \
222 NULL, \
223 NULL, \
224 CONFIG_SYS_POST_BSPEC2 \
225 }
226
227#define CONFIG_POST_BSPEC3 { \
228 "FPGA test", \
229 "fpga", \
230 "This test checks FPGA registers and memory.", \
231 POST_RAM | POST_ALWAYS | POST_MANUAL, \
232 &fpga_post_test, \
233 NULL, \
234 NULL, \
235 CONFIG_SYS_POST_BSPEC3 \
236 }
237
238#define CONFIG_POST_BSPEC4 { \
239 "GDC test", \
240 "gdc", \
241 "This test checks GDC registers and memory.", \
242 POST_RAM | POST_ALWAYS | POST_MANUAL,\
243 &gdc_post_test, \
244 NULL, \
245 NULL, \
246 CONFIG_SYS_POST_BSPEC4 \
247 }
248
249#define CONFIG_POST_BSPEC5 { \
250 "SYSMON1 test", \
251 "sysmon1", \
252 "This test checks GPIO_62_EPX pin indicating power failure.", \
253 POST_RAM | POST_MANUAL | POST_NORMAL | POST_SLOWTEST, \
254 &sysmon1_post_test, \
255 NULL, \
256 NULL, \
257 CONFIG_SYS_POST_BSPEC5 \
258 }
259
260#define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
261#define CONFIG_LOGBUFFER
262/* Reserve GPT0_COMP1-COMP5 for logbuffer header */
263#define CONFIG_ALT_LH_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP1)
264#define CONFIG_ALT_LB_ADDR (CONFIG_SYS_OCM_BASE)
265#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
Stefan Roese04386f62015-10-02 08:20:35 +0200[diff] [blame]266
267/*
268 * I2C
269 */
270#define CONFIG_SYS_I2C
271#define CONFIG_SYS_I2C_PPC4XX
272#define CONFIG_SYS_I2C_PPC4XX_CH0
273#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
274#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
275
276#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* RTC */
277#define CONFIG_SYS_I2C_EEPROM_CPU_ADDR 0x52 /* EEPROM (CPU Modul) */
278#define CONFIG_SYS_I2C_EEPROM_MB_ADDR 0x53 /* EEPROM AT24C128 (MainBoard) */
279#define CONFIG_SYS_I2C_DSPIC_ADDR 0x54 /* dsPIC */
280#define CONFIG_SYS_I2C_DSPIC_2_ADDR 0x55 /* dsPIC */
281#define CONFIG_SYS_I2C_DSPIC_KEYB_ADDR 0x56 /* dsPIC */
282#define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* dsPIC */
283
284#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
285#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel AT24C128 has */
286 /* 64 byte page write mode using*/
287 /* last 6 bits of the address */
288#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
289#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
290
291#define CONFIG_RTC_PCF8563 /* enable Philips PCF8563 RTC */
292#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */
293#define CONFIG_SYS_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */
294#define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* PIC I/O addr */
295
296#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_RTC_ADDR, \
297 CONFIG_SYS_I2C_EEPROM_CPU_ADDR,\
298 CONFIG_SYS_I2C_EEPROM_MB_ADDR, \
299 CONFIG_SYS_I2C_DSPIC_ADDR, \
300 CONFIG_SYS_I2C_DSPIC_2_ADDR, \
301 CONFIG_SYS_I2C_DSPIC_KEYB_ADDR,\
302 CONFIG_SYS_I2C_DSPIC_IO_ADDR }
303
304/*
305 * Pass open firmware flat tree
306 */
307#define CONFIG_OF_LIBFDT
308#define CONFIG_OF_BOARD_SETUP
309/* Update size in "reg" property of NOR FLASH device tree nodes */
310#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
311
312#define CONFIG_FIT /* enable FIT image support */
313
314#define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */
315
316#define CONFIG_PREBOOT "setenv bootdelay 15"
317
318#undef CONFIG_BOOTARGS
319
320#define CONFIG_EXTRA_ENV_SETTINGS \
321 "hostname=lwmon5\0" \
322 "netdev=eth0\0" \
323 "unlock=yes\0" \
324 "logversion=2\0" \
325 "nfsargs=setenv bootargs root=/dev/nfs rw " \
326 "nfsroot=${serverip}:${rootpath}\0" \
327 "ramargs=setenv bootargs root=/dev/ram rw\0" \
328 "addip=setenv bootargs ${bootargs} " \
329 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
330 ":${hostname}:${netdev}:off panic=1\0" \
331 "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
332 "addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\
333 "flash_nfs=run nfsargs addip addtty addmisc;" \
334 "bootm ${kernel_addr}\0" \
335 "flash_self=run ramargs addip addtty addmisc;" \
336 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
337 "net_nfs=tftp 200000 ${bootfile};" \
338 "run nfsargs addip addtty addmisc;bootm\0" \
339 "rootpath=/opt/eldk/ppc_4xxFP\0" \
340 "bootfile=/tftpboot/lwmon5/uImage\0" \
341 "kernel_addr=FC000000\0" \
342 "ramdisk_addr=FC180000\0" \
343 "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \
344 "update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;" \
345 "cp.b 200000 FFF80000 80000\0" \
346 "upd=run load update\0" \
347 "lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \
348 "autoscr 200000\0" \
349 ""
350#define CONFIG_BOOTCOMMAND "run flash_self"
351
352#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
353
354#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
355#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
356
357#define CONFIG_PPC4xx_EMAC
358#define CONFIG_IBM_EMAC4_V4 1
359#define CONFIG_MII 1 /* MII PHY management */
360#define CONFIG_PHY_ADDR 3 /* PHY address, See schematics */
361
362#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
363#define CONFIG_PHY_RESET_DELAY 300
364
365#define CONFIG_HAS_ETH0
366#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
367
368#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
369#define CONFIG_PHY1_ADDR 1
370
371/* Video console */
372#define CONFIG_VIDEO
373#define CONFIG_VIDEO_MB862xx
374#define CONFIG_VIDEO_MB862xx_ACCEL
375#define CONFIG_CFB_CONSOLE
376#define CONFIG_VIDEO_LOGO
377#define CONFIG_CONSOLE_EXTRA_INFO
378#define VIDEO_FB_16BPP_PIXEL_SWAP
379#define VIDEO_FB_16BPP_WORD_SWAP
380
381#define CONFIG_VGA_AS_SINGLE_DEVICE
382#define CONFIG_VIDEO_SW_CURSOR
383#define CONFIG_SPLASH_SCREEN
384
Stefan Roese04386f62015-10-02 08:20:35 +0200[diff] [blame]385/*
386 * USB/EHCI
387 */
388#define CONFIG_USB_EHCI /* Enable EHCI USB support */
389#define CONFIG_USB_EHCI_PPC4XX /* on PPC4xx platform */
390#define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300
391#define CONFIG_EHCI_MMIO_BIG_ENDIAN
392#define CONFIG_EHCI_DESC_BIG_ENDIAN
393#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
394#define CONFIG_USB_STORAGE
395
396/* Partitions */
397#define CONFIG_MAC_PARTITION
398#define CONFIG_DOS_PARTITION
399#define CONFIG_ISO_PARTITION
Stefan Roese04386f62015-10-02 08:20:35 +0200[diff] [blame]400
401/*
402 * BOOTP options
403 */
404#define CONFIG_BOOTP_BOOTFILESIZE
405#define CONFIG_BOOTP_BOOTPATH
406#define CONFIG_BOOTP_GATEWAY
407#define CONFIG_BOOTP_HOSTNAME
408
409/*
410 * Command line configuration.
411 */
412#define CONFIG_CMD_ASKENV
413#define CONFIG_CMD_DATE
414#define CONFIG_CMD_DHCP
415#define CONFIG_CMD_DIAG
416#define CONFIG_CMD_EEPROM
Stefan Roese04386f62015-10-02 08:20:35 +0200[diff] [blame]417#define CONFIG_CMD_FAT
418#define CONFIG_CMD_I2C
419#define CONFIG_CMD_IRQ
420#define CONFIG_CMD_MII
421#define CONFIG_CMD_PING
422#define CONFIG_CMD_REGINFO
423#define CONFIG_CMD_SDRAM
424
425#ifdef CONFIG_VIDEO
426#define CONFIG_CMD_BMP
427#endif
428
Stefan Roese04386f62015-10-02 08:20:35 +0200[diff] [blame]429#ifdef CONFIG_440EPX
430#define CONFIG_CMD_USB
431#endif
Stefan Roese04386f62015-10-02 08:20:35 +0200[diff] [blame]432
433/*
434 * Miscellaneous configurable options
435 */
436#define CONFIG_SUPPORT_VFAT
437
438#define CONFIG_SYS_LONGHELP /* undef to save memory */
439
440#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
441
442#if defined(CONFIG_CMD_KGDB)
443#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
444#else
445#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
446#endif
447#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
448#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
449#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
450
451#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
452#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
453
454#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
455#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
456
457#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
458#define CONFIG_LOOPW 1 /* enable loopw command */
459#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
460#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
461
462#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/
463
Stefan Roese04386f62015-10-02 08:20:35 +0200[diff] [blame]464#ifndef DEBUG
465#define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */
466#endif
467#define CONFIG_WD_PERIOD 40000 /* in usec */
468#define CONFIG_WD_MAX_RATE 66600 /* in ticks */
Stefan Roese04386f62015-10-02 08:20:35 +0200[diff] [blame]469
470/*
471 * For booting Linux, the board info and command line data
472 * have to be in the first 16 MB of memory, since this is
473 * the maximum mapped by the 40x Linux kernel during initialization.
474 */
475#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */
476#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
477
478/*
479 * External Bus Controller (EBC) Setup
480 */
481#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
482
483/* Memory Bank 0 (NOR-FLASH) initialization */
484#define CONFIG_SYS_EBC_PB0AP 0x03000280
485#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xfc000)
486
487/* Memory Bank 1 (Lime) initialization */
488#define CONFIG_SYS_EBC_PB1AP 0x01004380
489#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_LIME_BASE_0 | 0xbc000)
490
491/* Memory Bank 2 (FPGA) initialization */
492#define CONFIG_SYS_EBC_PB2AP 0x01004400
493#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA_BASE_0 | 0x1c000)
494
495/* Memory Bank 3 (FPGA2) initialization */
496#define CONFIG_SYS_EBC_PB3AP 0x01004400
497#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FPGA_BASE_1 | 0x1c000)
498
499#define CONFIG_SYS_EBC_CFG 0xb8400000
500
501/*
502 * Graphics (Fujitsu Lime)
503 */
504/* SDRAM Clock frequency adjustment register */
505#define CONFIG_SYS_LIME_SDRAM_CLOCK 0xC1FC0038
506#if 1 /* 133MHz is not tested enough, use 100MHz for now */
507/* Lime Clock frequency is to set 100MHz */
508#define CONFIG_SYS_LIME_CLOCK_100MHZ 0x00000
509#else
510/* Lime Clock frequency for 133MHz */
511#define CONFIG_SYS_LIME_CLOCK_133MHZ 0x10000
512#endif
513
514/* SDRAM Parameter register */
515#define CONFIG_SYS_LIME_MMR 0xC1FCFFFC
516/*
517 * SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
518 * and pixel flare on display when 133MHz was configured. According to
519 * SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed
520 * Grade
521 */
522#ifdef CONFIG_SYS_LIME_CLOCK_133MHZ
523#define CONFIG_SYS_MB862xx_MMR 0x414FB7F3
524#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_133MHZ
525#else
526#define CONFIG_SYS_MB862xx_MMR 0x414FB7F2
527#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_100MHZ
528#endif
529
530/*
531 * GPIO Setup
532 */
533#define CONFIG_SYS_GPIO_PHY1_RST 12
534#define CONFIG_SYS_GPIO_FLASH_WP 14
535#define CONFIG_SYS_GPIO_PHY0_RST 22
536#define CONFIG_SYS_GPIO_PERM_VOLT_FEED 49
537#define CONFIG_SYS_GPIO_DSPIC_READY 51
538#define CONFIG_SYS_GPIO_CAN_ENABLE 53
539#define CONFIG_SYS_GPIO_LSB_ENABLE 54
540#define CONFIG_SYS_GPIO_EEPROM_EXT_WP 55
541#define CONFIG_SYS_GPIO_HIGHSIDE 56
542#define CONFIG_SYS_GPIO_EEPROM_INT_WP 57
543#define CONFIG_SYS_GPIO_BOARD_RESET 58
544#define CONFIG_SYS_GPIO_LIME_S 59
545#define CONFIG_SYS_GPIO_LIME_RST 60
546#define CONFIG_SYS_GPIO_SYSMON_STATUS 62
547#define CONFIG_SYS_GPIO_WATCHDOG 63
548
Stefan Roese04386f62015-10-02 08:20:35 +0200[diff] [blame]549#define GPIO49_VAL 1
Stefan Roese04386f62015-10-02 08:20:35 +0200[diff] [blame]550
551/*
552 * PPC440 GPIO Configuration
553 */
554#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
555{ \
556/* GPIO Core 0 */ \
557{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
558{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
559{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
560{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
561{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
562{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
563{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
564{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
565{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
566{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
567{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
568{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
569{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
570{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
571{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
572{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO15 */ \
573{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \
574{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \
575{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \
576{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7) */ \
577{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
578{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
579{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
580{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
581{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2) */ \
582{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3) */ \
583{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
584{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
585{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \
586{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
587{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
588{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
589}, \
590{ \
591/* GPIO Core 1 */ \
592{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
593{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
594{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
595{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
596{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \
597{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
598{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
599{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
600{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
601{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
602{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
603{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
604{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
605{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
606{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
607{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
608{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
609{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO49_VAL}, /* GPIO49 Unselect via TraceSelect Bit */ \
610{GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
611{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
612{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
613{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
614{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
615{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \
616{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
617{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57 Unselect via TraceSelect Bit */ \
618{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
619{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
620{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
621{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
622{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
623{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
624} \
625}
626
627#if defined(CONFIG_CMD_KGDB)
628#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
629#endif
630
Stefan Roese04386f62015-10-02 08:20:35 +0200[diff] [blame]631#endif /* __CONFIG_H */