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Yoshihiro Shimoda320cf352013-12-18 16:03:44 +09001/*
2 * Configuation settings for the sh7753evb board
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#ifndef __SH7753EVB_H
10#define __SH7753EVB_H
11
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090012#define CONFIG_CPU_SH7753 1
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090013
Vladimir Zapolskiy18a40e82016-11-28 00:15:30 +020014#define CONFIG_DISPLAY_BOARDINFO
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090015#undef CONFIG_SHOW_BOOT_PROGRESS
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090016
17/* MEMORY */
18#define SH7753EVB_SDRAM_BASE (0x40000000)
19#define SH7753EVB_SDRAM_SIZE (512 * 1024 * 1024)
20
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090021#define CONFIG_SYS_PBSIZE 256
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090022#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
23
24/* SCIF */
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090025#define CONFIG_CONS_SCIF2 1
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090026
27#define CONFIG_SYS_MEMTEST_START (SH7753EVB_SDRAM_BASE)
28#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
29 480 * 1024 * 1024)
30#undef CONFIG_SYS_ALT_MEMTEST
31#undef CONFIG_SYS_MEMTEST_SCRATCH
32#undef CONFIG_SYS_LOADS_BAUD_CHANGE
33
34#define CONFIG_SYS_SDRAM_BASE (SH7753EVB_SDRAM_BASE)
35#define CONFIG_SYS_SDRAM_SIZE (SH7753EVB_SDRAM_SIZE)
36#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \
37 128 * 1024 * 1024)
38
39#define CONFIG_SYS_MONITOR_BASE 0x00000000
40#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
41#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
42#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
43
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090044/* Ether */
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090045#define CONFIG_SH_ETHER_USE_PORT 0
46#define CONFIG_SH_ETHER_PHY_ADDR 18
47#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
48#define CONFIG_SH_ETHER_USE_GETHER 1
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090049#define CONFIG_BITBANGMII
50#define CONFIG_BITBANGMII_MULTI
51#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII
52#define CONFIG_PHY_VITESSE
53
54#define SH7753EVB_ETHERNET_MAC_BASE_SPI 0x00090000
55#define SH7753EVB_SPI_SECTOR_SIZE (64 * 1024)
56#define SH7753EVB_ETHERNET_MAC_BASE SH7753EVB_ETHERNET_MAC_BASE_SPI
57#define SH7753EVB_ETHERNET_MAC_SIZE 17
58#define SH7753EVB_ETHERNET_NUM_CH 2
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090059
60/* SPI */
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090061#define CONFIG_SH_SPI_BASE 0xfe002000
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090062
63/* MMCIF */
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090064#define CONFIG_SH_MMCIF 1
65#define CONFIG_SH_MMCIF_ADDR 0xffcb0000
66#define CONFIG_SH_MMCIF_CLK 48000000
67
68/* ENV setting */
69#define CONFIG_ENV_IS_EMBEDDED
Yoshihiro Shimoda320cf352013-12-18 16:03:44 +090070#define CONFIG_ENV_SECT_SIZE (64 * 1024)
71#define CONFIG_ENV_ADDR (0x00080000)
72#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
73#define CONFIG_ENV_OVERWRITE 1
74#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
75#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
76#define CONFIG_EXTRA_ENV_SETTINGS \
77 "netboot=bootp; bootm\0"
78
79/* Board Clock */
80#define CONFIG_SYS_CLK_FREQ 48000000
81#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
82#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
83#define CONFIG_SYS_TMU_CLK_DIV 4
84#endif /* __SH7753EVB_H */