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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / d026dec8751378473b4f12eb87717c8059472b3e / . / arch / arm / cpu / ixp / u-boot.lds
blob: 9141199bedb4edac358c906627c95ac256c388d6 [file] [log] [blame]
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200[diff] [blame]1/*
Jean-Christophe PLAGNIOL-VILLARD10a451c2009-05-08 20:24:12 +0200[diff] [blame]2 * (C) Copyright 2000-2006
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200[diff] [blame]3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24OUTPUT_FORMAT("elf32-bigarm", "elf32-bigarm", "elf32-bigarm")
25OUTPUT_ARCH(arm)
26ENTRY(_start)
27SECTIONS
28{
29 . = 0x00000000;
30
31 . = ALIGN(4);
Jean-Christophe PLAGNIOL-VILLARD10a451c2009-05-08 20:24:12 +0200[diff] [blame]32 .text :
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200[diff] [blame]33 {
Albert ARIBAUDd026dec2013-06-11 14:17:33 +0200[diff] [blame^]34 *(.__image_copy_start)
Michael Schwingen66463e62011-05-23 00:00:03 +0200[diff] [blame]35 arch/arm/cpu/ixp/start.o(.text*)
36 *(.text*)
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200[diff] [blame]37 }
38
39 . = ALIGN(4);
Trent Piephof62fb992009-02-18 15:22:05 -0800[diff] [blame]40 .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200[diff] [blame]41
42 . = ALIGN(4);
Heiko Schocher2af0a092010-09-17 13:10:47 +0200[diff] [blame]43 .data : {
Michael Schwingen66463e62011-05-23 00:00:03 +0200[diff] [blame]44 *(.data*)
Heiko Schocher2af0a092010-09-17 13:10:47 +0200[diff] [blame]45 }
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200[diff] [blame]46
47 . = ALIGN(4);
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200[diff] [blame]48
49 . = .;
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200[diff] [blame]50
51 . = ALIGN(4);
Marek Vasut55675142012-10-12 10:27:03 +0000[diff] [blame]52 .u_boot_list : {
Albert ARIBAUDef123c52013-02-25 00:59:00 +0000[diff] [blame]53 KEEP(*(SORT(.u_boot_list*)));
Marek Vasut55675142012-10-12 10:27:03 +0000[diff] [blame]54 }
55
56 . = ALIGN(4);
Albert Aribaud3336ca62010-11-25 22:45:02 +0100[diff] [blame]57
Albert ARIBAUDd026dec2013-06-11 14:17:33 +0200[diff] [blame^]58 .image_copy_end :
59 {
60 *(.__image_copy_end)
61 }
Benoît Thébaudeau7086e912013-04-11 09:35:46 +0000[diff] [blame]62
Albert Aribaud3336ca62010-11-25 22:45:02 +0100[diff] [blame]63 .rel.dyn : {
64 __rel_dyn_start = .;
65 *(.rel*)
66 __rel_dyn_end = .;
67 }
68
Po-Yu Chuangf326cbb2011-03-01 23:02:04 +0000[diff] [blame]69 _end = .;
70
Albert ARIBAUDf84a7b82013-04-11 05:43:21 +0000[diff] [blame]71/*
72 * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
73 * __bss_base and __bss_limit are for linker only (overlay ordering)
74 */
75
Albert ARIBAUD3ebd1cb2013-02-25 00:58:59 +0000[diff] [blame]76 .bss_start __rel_dyn_start (OVERLAY) : {
77 KEEP(*(.__bss_start));
Albert ARIBAUDf84a7b82013-04-11 05:43:21 +0000[diff] [blame]78 __bss_base = .;
Albert ARIBAUD3ebd1cb2013-02-25 00:58:59 +0000[diff] [blame]79 }
80
Albert ARIBAUDf84a7b82013-04-11 05:43:21 +0000[diff] [blame]81 .bss __bss_base (OVERLAY) : {
Michael Schwingen66463e62011-05-23 00:00:03 +0200[diff] [blame]82 *(.bss*)
Albert Aribaud3336ca62010-11-25 22:45:02 +0100[diff] [blame]83 . = ALIGN(4);
Albert ARIBAUDf84a7b82013-04-11 05:43:21 +0000[diff] [blame]84 __bss_limit = .;
Albert ARIBAUD3ebd1cb2013-02-25 00:58:59 +0000[diff] [blame]85 }
Albert ARIBAUDf84a7b82013-04-11 05:43:21 +0000[diff] [blame]86 .bss_end __bss_limit (OVERLAY) : {
87 KEEP(*(.__bss_end));
Albert Aribaud3336ca62010-11-25 22:45:02 +0100[diff] [blame]88 }
89
Albert ARIBAUD09d81182013-06-11 14:17:31 +0200[diff] [blame]90 /DISCARD/ : { *(.dynsym) }
Albert Aribaud3336ca62010-11-25 22:45:02 +0100[diff] [blame]91 /DISCARD/ : { *(.dynstr*) }
92 /DISCARD/ : { *(.dynamic*) }
93 /DISCARD/ : { *(.plt*) }
94 /DISCARD/ : { *(.interp*) }
95 /DISCARD/ : { *(.gnu*) }
Wolfgang Denkba94a1b2006-05-30 15:56:48 +0200[diff] [blame]96}