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Wolfgang Denk46263f22013-07-28 22:12:45 +02001/*
Wolfgang Denk1b387ef2013-09-17 11:24:06 +02002 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
Wolfgang Denk46263f22013-07-28 22:12:45 +02003 */
wdenkfe8c2802002-11-03 00:38:21 +00004
5/*----------------------------------------------------------------------------- */
6/* Function: ext_bus_cntlr_init */
7/* Description: Initializes the External Bus Controller for the external */
8/* peripherals. IMPORTANT: For pass1 this code must run from */
9/* cache since you can not reliably change a peripheral banks */
10/* timing register (pbxap) while running code from that bank. */
11/* For ex., since we are running from ROM on bank 0, we can NOT */
12/* execute the code that modifies bank 0 timings from ROM, so */
13/* we run it from cache. */
14/* Bank 0 - Flash and SRAM */
15/* Bank 1 - NVRAM/RTC */
16/* Bank 2 - Keyboard/Mouse controller */
17/* Bank 3 - IR controller */
18/* Bank 4 - not used */
19/* Bank 5 - not used */
20/* Bank 6 - not used */
21/* Bank 7 - FPGA registers */
22/*-----------------------------------------------------------------------------#include <config.h> */
Stefan Roeseb36df562010-09-09 19:18:00 +020023#include <asm/ppc4xx.h>
wdenkfe8c2802002-11-03 00:38:21 +000024
wdenkfe8c2802002-11-03 00:38:21 +000025#include <ppc_asm.tmpl>
26#include <ppc_defs.h>
27
28#include <asm/cache.h>
29#include <asm/mmu.h>
30
31/* CRAY - L1: only nominally a 'walnut', since ext.Bus.Cntlr is all empty */
32/* except for #1 which we use for DMA'ing to IOCA-like things, so the */
33/* control registers to set that up are determined by what we've */
34/* empirically discovered work there. */
35
wdenk8bde7f72003-06-27 21:31:46 +000036 .globl ext_bus_cntlr_init
wdenkfe8c2802002-11-03 00:38:21 +000037ext_bus_cntlr_init:
wdenk8bde7f72003-06-27 21:31:46 +000038 mflr r4 /* save link register */
39 bl ..getAddr
wdenkfe8c2802002-11-03 00:38:21 +000040..getAddr:
wdenk8bde7f72003-06-27 21:31:46 +000041 mflr r3 /* get address of ..getAddr */
42 mtlr r4 /* restore link register */
43 addi r4,0,14 /* set ctr to 10; used to prefetch */
44 mtctr r4 /* 10 cache lines to fit this function */
45 /* in cache (gives us 8x10=80 instrctns) */
wdenkfe8c2802002-11-03 00:38:21 +000046..ebcloop:
wdenk8bde7f72003-06-27 21:31:46 +000047 icbt r0,r3 /* prefetch cache line for addr in r3 */
48 addi r3,r3,32 /* move to next cache line */
49 bdnz ..ebcloop /* continue for 10 cache lines */
wdenkfe8c2802002-11-03 00:38:21 +000050
wdenk8bde7f72003-06-27 21:31:46 +000051 /*------------------------------------------------------------------- */
52 /* Delay to ensure all accesses to ROM are complete before changing */
wdenkfe8c2802002-11-03 00:38:21 +000053 /* bank 0 timings. 200usec should be enough. */
wdenk8bde7f72003-06-27 21:31:46 +000054 /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
55 /*------------------------------------------------------------------- */
wdenkfe8c2802002-11-03 00:38:21 +000056 addis r3,0,0x0
wdenk8bde7f72003-06-27 21:31:46 +000057 ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
58 mtctr r3
wdenkfe8c2802002-11-03 00:38:21 +000059..spinlp:
wdenk8bde7f72003-06-27 21:31:46 +000060 bdnz ..spinlp /* spin loop */
wdenkfe8c2802002-11-03 00:38:21 +000061
62
wdenk8bde7f72003-06-27 21:31:46 +000063 /*---------------------------------------------------------------------- */
64 /* Peripheral Bank 0 (Flash) initialization */
65 /*---------------------------------------------------------------------- */
wdenkfe8c2802002-11-03 00:38:21 +000066 /* 0x7F8FFE80 slowest boot */
Stefan Roesed1c3b272009-09-09 16:25:29 +020067 addi r4,0,PB1AP
68 mtdcr EBC0_CFGADDR,r4
wdenk8bde7f72003-06-27 21:31:46 +000069 addis r4,0,0x9B01
70 ori r4,r4,0x5480
Stefan Roesed1c3b272009-09-09 16:25:29 +020071 mtdcr EBC0_CFGDATA,r4
wdenkfe8c2802002-11-03 00:38:21 +000072
Stefan Roesed1c3b272009-09-09 16:25:29 +020073 addi r4,0,PB0CR
74 mtdcr EBC0_CFGADDR,r4
wdenk8bde7f72003-06-27 21:31:46 +000075 addis r4,0,0xFFC5 /* BAS=0xFFC,BS=0x4(4MB),BU=0x3(R/W), */
76 ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
Stefan Roesed1c3b272009-09-09 16:25:29 +020077 mtdcr EBC0_CFGDATA,r4
wdenkfe8c2802002-11-03 00:38:21 +000078
wdenk8bde7f72003-06-27 21:31:46 +000079 blr
wdenkfe8c2802002-11-03 00:38:21 +000080
wdenk8bde7f72003-06-27 21:31:46 +000081 /*---------------------------------------------------------------------- */
82 /* Peripheral Bank 1 (NVRAM/RTC) initialization */
wdenkfe8c2802002-11-03 00:38:21 +000083 /* CRAY:the L1 has NOT this bank, it is tied to SV2/IOCA/etc/ instead */
84 /* and we do DMA on it. The ConfigurationRegister part is threfore */
85 /* almost arbitrary, except that our linux driver needs to know the */
86 /* address, but it can query, it.. */
87 /* */
88 /* The AccessParameter is CRITICAL, */
89 /* thouch, since it needs to agree with the electrical timings on the */
90 /* IOCA parallel interface. That value is: 0x0185,4380 */
91 /* BurstModeEnable BME=0 */
92 /* TransferWait TWT=3 */
93 /* ChipSelectOnTiming CSN=1 */
94 /* OutputEnableOnTimimg OEN=1 */
95 /* WriteByteEnableOnTiming WBN=1 */
96 /* WriteByteEnableOffTiming WBF=0 */
97 /* TransferHold TH=1 */
98 /* ReadyEnable RE=1 */
99 /* SampleOnReady SOR=1 */
100 /* ByteEnableMode BEM=0 */
101 /* ParityEnable PEN=0 */
102 /* all reserved bits=0 */
wdenk8bde7f72003-06-27 21:31:46 +0000103 /*---------------------------------------------------------------------- */
104 /*---------------------------------------------------------------------- */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200105 addi r4,0,PB1AP
106 mtdcr EBC0_CFGADDR,r4
wdenk8bde7f72003-06-27 21:31:46 +0000107 addis r4,0,0x0185 /* hiword */
108 ori r4,r4,0x4380 /* loword */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200109 mtdcr EBC0_CFGDATA,r4
wdenkfe8c2802002-11-03 00:38:21 +0000110
Stefan Roesed1c3b272009-09-09 16:25:29 +0200111 addi r4,0,PB1CR
112 mtdcr EBC0_CFGADDR,r4
wdenk8bde7f72003-06-27 21:31:46 +0000113 addis r4,0,0xF001 /* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W), */
114 ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200115 mtdcr EBC0_CFGDATA,r4
wdenkfe8c2802002-11-03 00:38:21 +0000116
wdenk8bde7f72003-06-27 21:31:46 +0000117 blr