| chao zeng | ed57c40 | 2023-02-28 19:19:22 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (c) Siemens AG, 2018-2023 |
| 4 | * |
| 5 | * Authors: |
| 6 | * Chao Zeng <chao.zeng@siemens.com> |
| 7 | * Jan Kiszka <jan.kiszka@siemens.com> |
| 8 | * |
| 9 | * AM6548-based (quad-core) IOT2050 M.2 variant (based on Advanced Product |
| 10 | * Generation 2), 2 GB RAM, 16 GB eMMC, USB-serial converter on connector X30 |
| 11 | * |
| 12 | * Product homepage: |
| 13 | * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html |
| 14 | */ |
| 15 | |
| 16 | #include "k3-am6548-iot2050-advanced-common.dtsi" |
| 17 | #include "k3-am65-iot2050-common-pg2.dtsi" |
| 18 | |
| 19 | / { |
| 20 | compatible = "siemens,iot2050-advanced-m2", "ti,am654"; |
| 21 | model = "SIMATIC IOT2050 Advanced M2"; |
| 22 | }; |
| 23 | |
| 24 | &mcu_r5fss0 { |
| 25 | /* lock-step mode not supported on this board */ |
| 26 | ti,cluster-mode = <0>; |
| 27 | }; |
| 28 | |
| 29 | &main_pmx0 { |
| 30 | main_m2_enable_pins_default: main-m2-enable-pins-default { |
| 31 | pinctrl-single,pins = < |
| 32 | AM65X_IOPAD(0x01c4, PIN_INPUT_PULLUP, 7) /* (AH13) GPIO1_17 */ |
| 33 | >; |
| 34 | }; |
| 35 | |
| 36 | main_bkey_pcie_reset: main-bkey-pcie-reset { |
| 37 | pinctrl-single,pins = < |
| 38 | AM65X_IOPAD(0x01bc, PIN_OUTPUT_PULLUP, 7) /* (AG13) GPIO1_15 */ |
| 39 | >; |
| 40 | }; |
| 41 | |
| 42 | main_pmx0_m2_config_pins_default: main-pmx0-m2-config-pins-default { |
| 43 | pinctrl-single,pins = < |
| 44 | AM65X_IOPAD(0x01c8, PIN_INPUT_PULLUP, 7) /* (AE13) GPIO1_18 */ |
| 45 | AM65X_IOPAD(0x01cc, PIN_INPUT_PULLUP, 7) /* (AD13) GPIO1_19 */ |
| 46 | >; |
| 47 | }; |
| 48 | |
| 49 | main_m2_pcie_mux_control: main-m2-pcie-mux-control { |
| 50 | pinctrl-single,pins = < |
| 51 | AM65X_IOPAD(0x0148, PIN_INPUT_PULLUP, 7) /* (AG22) GPIO0_82 */ |
| 52 | AM65X_IOPAD(0x0160, PIN_INPUT_PULLUP, 7) /* (AE20) GPIO0_88 */ |
| 53 | AM65X_IOPAD(0x0164, PIN_INPUT_PULLUP, 7) /* (AF19) GPIO0_89 */ |
| 54 | >; |
| 55 | }; |
| 56 | }; |
| 57 | |
| 58 | &main_pmx1 { |
| 59 | main_pmx1_m2_config_pins_default: main-pmx1-m2-config-pins-default { |
| 60 | pinctrl-single,pins = < |
| 61 | AM65X_IOPAD(0x0018, PIN_INPUT_PULLUP, 7) /* (B22) GPIO1_88 */ |
| 62 | AM65X_IOPAD(0x001c, PIN_INPUT_PULLUP, 7) /* (C23) GPIO1_89 */ |
| 63 | >; |
| 64 | }; |
| 65 | }; |
| 66 | |
| 67 | &main_gpio0 { |
| 68 | pinctrl-names = "default"; |
| 69 | pinctrl-0 = < |
| 70 | &main_m2_pcie_mux_control |
| 71 | &arduino_io_d4_to_d9_pins_default |
| 72 | >; |
| 73 | }; |
| 74 | |
| 75 | &main_gpio1 { |
| 76 | pinctrl-names = "default"; |
| 77 | pinctrl-0 = < |
| 78 | &main_m2_enable_pins_default |
| 79 | &main_pmx0_m2_config_pins_default |
| 80 | &main_pmx1_m2_config_pins_default |
| 81 | &cp2102n_reset_pin_default |
| 82 | >; |
| 83 | }; |
| 84 | |
| 85 | /* |
| 86 | * Base configuration for B-key slot with PCIe x2, E-key with USB 2.0 only. |
| 87 | * Firmware switches to other modes via device tree overlays. |
| 88 | */ |
| 89 | |
| 90 | &serdes0 { |
| 91 | assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; |
| 92 | assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>; |
| 93 | }; |
| 94 | |
| 95 | &pcie0_rc { |
| 96 | pinctrl-names = "default"; |
| 97 | pinctrl-0 = <&main_bkey_pcie_reset>; |
| 98 | |
| 99 | num-lanes = <2>; |
| 100 | phys = <&serdes0 PHY_TYPE_PCIE 1>, <&serdes1 PHY_TYPE_PCIE 1>; |
| 101 | phy-names = "pcie-phy0","pcie-phy1"; |
| 102 | reset-gpios = <&main_gpio1 15 GPIO_ACTIVE_HIGH>; |
| 103 | status = "okay"; |
| 104 | }; |
| 105 | |
| 106 | &pcie1_rc { |
| 107 | status = "disabled"; |
| 108 | }; |
| 109 | |
| 110 | &dwc3_0 { |
| 111 | assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ |
| 112 | <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */ |
| 113 | /delete-property/ phys; |
| 114 | /delete-property/ phy-names; |
| 115 | }; |
| 116 | |
| 117 | &usb0 { |
| 118 | maximum-speed = "high-speed"; |
| 119 | /delete-property/ snps,dis-u1-entry-quirk; |
| 120 | /delete-property/ snps,dis-u2-entry-quirk; |
| 121 | }; |