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Stefan Roese5568e612005-11-22 13:20:42 +01001/*
Stefan Roese62534be2006-03-17 10:28:24 +01002 * (C) Copyright 2005-2006
Stefan Roese5568e612005-11-22 13:20:42 +01003 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26/************************************************************************
27 * board/config_p3p440.h - configuration for Prodrive P3P440
28 ***********************************************************************/
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
33/*-----------------------------------------------------------------------
34 * High Level Configuration Options
35 *----------------------------------------------------------------------*/
36#define CONFIG_P3P440 1 /* Board is P3P440 */
37#define CONFIG_440GP 1 /* Specifc GP support */
38#define CONFIG_4xx 1 /* ... PPC4xx family */
39#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
40#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
41#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
42
43/*-----------------------------------------------------------------------
44 * Base addresses -- Note these are effective addresses where the
45 * actual resources get mapped (not physical addresses)
46 *----------------------------------------------------------------------*/
47#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
48#define CFG_FLASH_BASE 0xff800000 /* start of FLASH */
49#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */
50#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
51#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
52#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
53#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
54
55#define CFG_USB_BASE (CFG_PERIPHERAL_BASE + 0x00000000)
56
57/*-----------------------------------------------------------------------
58 * Initial RAM & stack pointer (placed in internal SRAM)
59 *----------------------------------------------------------------------*/
60#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
61#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
62#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
63
64#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
65#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
66
67#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
68#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
69
70/*-----------------------------------------------------------------------
71 * DDR SDRAM
72 *----------------------------------------------------------------------*/
73#define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0*/
Stefan Roese62534be2006-03-17 10:28:24 +010074#define CONFIG_SDRAM_ECC /* enable ECC support */
75#define CFG_SDRAM_TABLE { \
76 {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \
77 {(64 << 20), 12, 0x00082001}} /* 64MB mode 2, 12x9(4) */
Stefan Roese5568e612005-11-22 13:20:42 +010078
79/*-----------------------------------------------------------------------
80 * Serial Port
81 *----------------------------------------------------------------------*/
82#undef CFG_EXT_SERIAL_CLOCK
83#define CONFIG_BAUDRATE 115200
84
85#define CFG_BAUDRATE_TABLE \
86 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
87 57600, 115200, 230400, 460800, 921600 }
88
89/*-----------------------------------------------------------------------
90 * I2C
91 *----------------------------------------------------------------------*/
92#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
93#undef CONFIG_SOFT_I2C /* I2C bit-banged */
94#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
95#define CFG_I2C_SLAVE 0x7F
96#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
97
98/*-----------------------------------------------------------------------
99 * I2C RTC
100 *----------------------------------------------------------------------*/
101#define CONFIG_RTC_MAX6900 1 /* MAX6900 RTC */
102
103/*-----------------------------------------------------------------------
104 * I2C EEPROM (PCF8594C) for environment
105 *----------------------------------------------------------------------*/
106#define CFG_I2C_EEPROM_ADDR 0x54 /* EEPROM PCF8594C */
107#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
108/* mask of address bits that overflow into the "EEPROM chip address" */
109#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
110#define CFG_EEPROM_PAGE_WRITE_BITS 3 /* The Philips PCF8594C has */
111 /* 8 byte page write mode using */
112 /* last 3 bits of the address */
113#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 40 /* and takes up to 40 msec */
114#define CFG_EEPROM_PAGE_WRITE_ENABLE
115
116/*-----------------------------------------------------------------------
117 * Default configuration (environment varibles...)
118 *----------------------------------------------------------------------*/
119#define CONFIG_PREBOOT "echo;" \
120 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
121 "echo"
122
123#undef CONFIG_BOOTARGS
124
125#define CONFIG_EXTRA_ENV_SETTINGS \
126 "netdev=eth0\0" \
127 "hostname=p3p440\0" \
128 "nfsargs=setenv bootargs root=/dev/nfs rw " \
129 "nfsroot=${serverip}:${rootpath}\0" \
130 "ramargs=setenv bootargs root=/dev/ram rw\0" \
131 "addip=setenv bootargs ${bootargs} " \
132 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
133 ":${hostname}:${netdev}:off panic=1\0" \
134 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
135 "flash_nfs=run nfsargs addip addtty;" \
136 "bootm ${kernel_addr}\0" \
137 "flash_self=run ramargs addip addtty;" \
138 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
139 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
140 "bootm\0" \
141 "rootpath=/opt/eldk/ppc_4xx\0" \
142 "bootfile=/tftpboot/p3p440/uImage\0" \
143 "kernel_addr=ff800000\0" \
144 "ramdisk_addr=ff810000\0" \
145 "load=tftp 100000 /tftpboot/p3p440/u-boot.bin\0" \
146 "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
147 "cp.b 100000 fffc0000 40000;" \
148 "setenv filesize;saveenv\0" \
149 "upd=run load;run update\0" \
Stefan Roese2662b402006-04-01 13:41:03 +0200150 "unlock=yes\0" \
Stefan Roese5568e612005-11-22 13:20:42 +0100151 ""
152#define CONFIG_BOOTCOMMAND "run net_nfs"
153
154#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
155
156#define CONFIG_BAUDRATE 115200
157
158#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
159#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
160
161#define CONFIG_MII 1 /* MII PHY management */
162#define CONFIG_PHY_ADDR 0x1c /* PHY address */
163#define CONFIG_HAS_ETH1
164#define CONFIG_PHY1_ADDR 0x1d /* EMAC1 PHY address */
165#define CONFIG_NET_MULTI 1
166#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
167
168#define CONFIG_NETCONSOLE /* include NetConsole support */
169
170#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
171 CFG_CMD_ASKENV | \
172 CFG_CMD_DATE | \
173 CFG_CMD_DHCP | \
174 CFG_CMD_DIAG | \
175 CFG_CMD_ELF | \
176 CFG_CMD_I2C | \
177 CFG_CMD_IRQ | \
178 CFG_CMD_MII | \
179 CFG_CMD_NET | \
180 CFG_CMD_NFS | \
181 CFG_CMD_PCI | \
182 CFG_CMD_PING | \
183 CFG_CMD_REGINFO | \
184 CFG_CMD_EEPROM | \
185 CFG_CMD_SNTP )
186
187/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
188#include <cmd_confdefs.h>
189
190#undef CONFIG_WATCHDOG /* watchdog disabled */
191
192/*-----------------------------------------------------------------------
193 * Miscellaneous configurable options
194 *----------------------------------------------------------------------*/
195#define CFG_LONGHELP /* undef to save memory */
196#define CFG_PROMPT "=> " /* Monitor Command Prompt */
197#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
198#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
199#else
200#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
201#endif
202#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
203#define CFG_MAXARGS 16 /* max number of command args */
204#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
205
206#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
207#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
208
209#define CFG_LOAD_ADDR 0x100000 /* default load address */
210#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
211
212#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
213
214#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
215#define CONFIG_LOOPW 1 /* enable loopw command */
216#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
217#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
218
219/*-----------------------------------------------------------------------
220 * PCI stuff
221 *----------------------------------------------------------------------*/
222/* General PCI */
223#define CONFIG_PCI /* include pci support */
224#define CONFIG_PCI_PNP /* do pci plug-and-play */
225#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
226#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
227
228/* Board-specific PCI */
229#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
230#define CFG_PCI_TARGET_INIT /* let board init pci target */
231
232#define CONFIG_DISABLE_PISE_TEST /* disable PISE test (PCIX only)*/
233
234#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
235#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
236
237/*-----------------------------------------------------------------------
238 * External Bus Controller (EBC) Setup
239 *----------------------------------------------------------------------*/
240#define CFG_FLASH0 0xFF800000
241#define CFG_FLASH1 0xFF000000
242#define CFG_FLASH2 0xFE800000
243#define CFG_FLASH3 0xFE000000
244#define CFG_USB 0xF0000000
245
246/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
247#define CFG_EBC_PB0AP 0x03050200
248#define CFG_EBC_PB0CR (CFG_FLASH0 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
249
250/* Memory Bank 1 (Flash Bank 1, NOR-FLASH) initialization */
251#define CFG_EBC_PB1AP 0x03050200
252#define CFG_EBC_PB1CR (CFG_FLASH1 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
253
254/* Memory Bank 2 (Flash Bank 2, NOR-FLASH) initialization */
255#define CFG_EBC_PB2AP 0x03050200
256#define CFG_EBC_PB2CR (CFG_FLASH2 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
257
258/* Memory Bank 3 (Flash Bank 3, NOR-FLASH) initialization */
259#define CFG_EBC_PB3AP 0x03050200
260#define CFG_EBC_PB3CR (CFG_FLASH3 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
261
262/* Memory Bank 7 (USB controller) initialization */
263#define CFG_EBC_PB7AP 0x02015000
264#define CFG_EBC_PB7CR (CFG_USB | 0xFE000) /* BAS=0xF00,BS=128MB,BU=R/W,BW=16bit*/
265
266/*-----------------------------------------------------------------------
267 * FLASH related
268 *----------------------------------------------------------------------*/
269#define CFG_FLASH_CFI /* The flash is CFI compatible */
270#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
271
272#define CFG_FLASH_BANKS_LIST { CFG_FLASH3, CFG_FLASH2, CFG_FLASH1, CFG_FLASH0 }
273
274#define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */
275#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
276
277#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
278#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
279
Stefan Roese62534be2006-03-17 10:28:24 +0100280#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
Wolfgang Denk71b405d2006-04-06 00:16:58 +0200281#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
Stefan Roese62534be2006-03-17 10:28:24 +0100282
Stefan Roese5568e612005-11-22 13:20:42 +0100283#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
284#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
285
286#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
287
288#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
289#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
290#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
291
292/* Address and size of Redundant Environment Sector */
293#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
294#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
295
296/*
297 * For booting Linux, the board info and command line data
298 * have to be in the first 8 MB of memory, since this is
299 * the maximum mapped by the Linux kernel during initialization.
300 */
301#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
302/*-----------------------------------------------------------------------
303 * Cache Configuration
304 */
305#define CFG_DCACHE_SIZE (32<<10) /* For AMCC 405 CPUs */
306#define CFG_CACHELINE_SIZE 32 /* ... */
307#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
308#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
309#endif
310
311/*
312 * Internal Definitions
313 *
314 * Boot Flags
315 */
316#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
317#define BOOTFLAG_WARM 0x02 /* Software reboot */
318
319#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
320#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
321#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
322#endif
323#endif /* __CONFIG_H */