| wdenk | efee170 | 2002-07-20 20:14:13 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2000 Murray Jensen <Murray.Jensen@cmst.csiro.au> |
| 3 | * |
| 4 | * See file CREDITS for list of people who contributed to this |
| 5 | * project. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 20 | * MA 02111-1307USA |
| 21 | */ |
| 22 | |
| 23 | /* note - this won't work with the 74xx cpus. needs more work [josh] */ |
| 24 | |
| 25 | #include <config.h> |
| 26 | #include <command.h> |
| 27 | #include <74xx_7xx.h> |
| 28 | #include <version.h> |
| 29 | |
| 30 | #include <ppc_asm.tmpl> |
| 31 | #include <ppc_defs.h> |
| 32 | |
| 33 | #include <asm/cache.h> |
| 34 | #include <asm/mmu.h> |
| 35 | |
| 36 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
| 37 | |
| 38 | /* |
| 39 | * cache flushing routines for kgdb |
| 40 | */ |
| 41 | |
| 42 | .globl kgdb_flush_cache_all |
| 43 | kgdb_flush_cache_all: |
| 44 | lis r3, IDC_INVALL@h |
| 45 | mtspr DC_CST, r3 |
| 46 | sync |
| 47 | lis r3, IDC_INVALL@h |
| 48 | mtspr IC_CST, r3 |
| 49 | SYNC |
| 50 | blr |
| 51 | |
| 52 | .globl kgdb_flush_cache_range |
| 53 | kgdb_flush_cache_range: |
| 54 | li r5,CFG_CACHELINE_SIZE-1 |
| 55 | andc r3,r3,r5 |
| 56 | subf r4,r3,r4 |
| 57 | add r4,r4,r5 |
| 58 | srwi. r4,r4,CFG_CACHELINE_SHIFT |
| 59 | beqlr |
| 60 | mtctr r4 |
| 61 | mr r6,r3 |
| 62 | 1: dcbst 0,r3 |
| 63 | addi r3,r3,CFG_CACHELINE_SIZE |
| 64 | bdnz 1b |
| 65 | sync /* wait for dcbst's to get to ram */ |
| 66 | mtctr r4 |
| 67 | 2: icbi 0,r6 |
| 68 | addi r6,r6,CFG_CACHELINE_SIZE |
| 69 | bdnz 2b |
| 70 | SYNC |
| 71 | blr |
| 72 | |
| 73 | #endif /* CFG_CMD_KGDB */ |