blob: 399be23e1e22ff510f77161f951ab67cf507ac75 [file] [log] [blame]
Michael Schwingenea99e8f2008-01-16 19:50:37 +01001/*
2 * (C) Copyright 2007
3 * Michael Schwingen, michael@schwingen.org
4 *
5 * (C) Copyright 2006
6 * Stefan Roese, DENX Software Engineering, sr@denx.de.
7 *
8 * (C) Copyright 2002
9 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
10 *
11 * (C) Copyright 2002
12 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
13 * Marius Groeger <mgroeger@sysgo.de>
14 *
15 * See file CREDITS for list of people who contributed to this
16 * project.
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * MA 02111-1307 USA
32 */
33
34#include <common.h>
35#include <command.h>
36#include <malloc.h>
37#include <asm/arch/ixp425.h>
38#include <asm/io.h>
39#include <miiphy.h>
40
41#include "actux1_hw.h"
42
43DECLARE_GLOBAL_DATA_PTR;
44
45int board_init (void)
46{
47 gd->bd->bi_arch_number = MACH_TYPE_ACTUX1;
48
49 /* adress of boot parameters */
50 gd->bd->bi_boot_params = 0x00000100;
51
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052 GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
53 GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST);
Michael Schwingenea99e8f2008-01-16 19:50:37 +010054
55 /* Setup GPIO's for PCI INTA */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056 GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_PCI1_INTA);
57 GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_PCI1_INTA);
Michael Schwingenea99e8f2008-01-16 19:50:37 +010058
59 /* Setup GPIO's for 33MHz clock output */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060 GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK);
61 GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK);
Michael Schwingenea99e8f2008-01-16 19:50:37 +010062 *IXP425_GPIO_GPCLKR = 0x011001FF;
63
64 /* CS5: Debug port */
65 *IXP425_EXP_CS5 = 0x9d520003;
66 /* CS6: HwRel */
67 *IXP425_EXP_CS6 = 0x81860001;
68 /* CS7: LEDs */
69 *IXP425_EXP_CS7 = 0x80900003;
70
71 udelay (533);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072 GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
Michael Schwingenea99e8f2008-01-16 19:50:37 +010073
74 ACTUX1_LED1 (2);
75 ACTUX1_LED2 (2);
76 ACTUX1_LED3 (0);
77 ACTUX1_LED4 (0);
78 ACTUX1_LED5 (0);
79 ACTUX1_LED6 (0);
80 ACTUX1_LED7 (0);
81
82 ACTUX1_HS (ACTUX1_HS_DCD);
83
84 return 0;
85}
86
87/*
88 * Check Board Identity
89 */
90int checkboard (void)
91{
Michael Schwingenea99e8f2008-01-16 19:50:37 +010092 char *s = getenv ("serial#");
93
94 puts ("Board: AcTux-1 rev.");
95 putc (ACTUX1_BOARDREL + 'A' - 1);
96
97 if (s != NULL) {
98 puts (", serial# ");
99 puts (s);
100 }
101 putc ('\n');
102
103 return (0);
104}
105
106/*************************************************************************
107 * get_board_rev() - setup to pass kernel board revision information
108 * 0 = reserved
109 * 1 = Rev. A
110 * 2 = Rev. B
111 *************************************************************************/
112u32 get_board_rev (void)
113{
114 return ACTUX1_BOARDREL;
115}
116
117int dram_init (void)
118{
119 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
120 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
121
122 return (0);
123}
124
125#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
126extern struct pci_controller hose;
127extern void pci_ixp_init (struct pci_controller *hose);
128
129void pci_init_board (void)
130{
131 extern void pci_ixp_init (struct pci_controller *hose);
132 pci_ixp_init (&hose);
133}
134#endif
135
136void reset_phy (void)
137{
138 u16 id1, id2;
139
140 /* initialize the PHY */
141 miiphy_reset ("NPE0", CONFIG_PHY_ADDR);
142
143 miiphy_read ("NPE0", CONFIG_PHY_ADDR, PHY_PHYIDR1, &id1);
144 miiphy_read ("NPE0", CONFIG_PHY_ADDR, PHY_PHYIDR2, &id2);
145
146 id2 &= 0xFFF0; /* mask out revision bits */
147
148 if (id1 == 0x13 && id2 == 0x78e0) {
149 /*
150 * LXT971/LXT972 PHY: set LED outputs:
151 * LED1(green) = Link/ACT,
152 * LED2 (unused) = LINK,
153 * LED3(red) = Coll
154 */
155 miiphy_write ("NPE0", CONFIG_PHY_ADDR, 20, 0xD432);
156 } else if (id1 == 0x143 && id2 == 0xbc30) {
157 /* BCM5241: default values are OK */
158 } else
159 printf ("unknown ethernet PHY ID: %x %x\n", id1, id2);
160}