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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Kever Yang79c83062016-07-18 17:00:58 +08002/*
3 * (C) Copyright 2016 Fuzhou Rockchip Electronics Co., Ltd
4 *
5 * Rockchip SD Host Controller Interface
Kever Yang79c83062016-07-18 17:00:58 +08006 */
7
8#include <common.h>
9#include <dm.h>
Kever Yangc2868212017-02-13 17:38:57 +080010#include <dt-structs.h>
Simon Glass61b29b82020-02-03 07:36:15 -070011#include <linux/err.h>
Masahiro Yamadab08c8c42018-03-05 01:20:11 +090012#include <linux/libfdt.h>
Kever Yang79c83062016-07-18 17:00:58 +080013#include <malloc.h>
Kever Yangc2868212017-02-13 17:38:57 +080014#include <mapmem.h>
Kever Yang79c83062016-07-18 17:00:58 +080015#include <sdhci.h>
Kever Yang39fbb562016-12-28 11:32:35 +080016#include <clk.h>
Kever Yang79c83062016-07-18 17:00:58 +080017
18/* 400KHz is max freq for card ID etc. Use that as min */
19#define EMMC_MIN_FREQ 400000
20
21struct rockchip_sdhc_plat {
Kever Yangc2868212017-02-13 17:38:57 +080022#if CONFIG_IS_ENABLED(OF_PLATDATA)
23 struct dtd_rockchip_rk3399_sdhci_5_1 dtplat;
24#endif
Kever Yang79c83062016-07-18 17:00:58 +080025 struct mmc_config cfg;
26 struct mmc mmc;
27};
28
29struct rockchip_sdhc {
30 struct sdhci_host host;
31 void *base;
32};
33
34static int arasan_sdhci_probe(struct udevice *dev)
35{
36 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
Simon Glassc69cda22020-12-03 16:55:20 -070037 struct rockchip_sdhc_plat *plat = dev_get_plat(dev);
Kever Yang79c83062016-07-18 17:00:58 +080038 struct rockchip_sdhc *prv = dev_get_priv(dev);
39 struct sdhci_host *host = &prv->host;
Kever Yang39fbb562016-12-28 11:32:35 +080040 int max_frequency, ret;
41 struct clk clk;
42
Kever Yangc2868212017-02-13 17:38:57 +080043#if CONFIG_IS_ENABLED(OF_PLATDATA)
44 struct dtd_rockchip_rk3399_sdhci_5_1 *dtplat = &plat->dtplat;
Kever Yang39fbb562016-12-28 11:32:35 +080045
Kever Yangc2868212017-02-13 17:38:57 +080046 host->name = dev->name;
Kever Yang5184dad2017-09-07 11:20:50 +080047 host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
Kever Yangc2868212017-02-13 17:38:57 +080048 max_frequency = dtplat->max_frequency;
Walter Lozano51f12632020-06-25 01:10:13 -030049 ret = clk_get_by_driver_info(dev, dtplat->clocks, &clk);
Kever Yangc2868212017-02-13 17:38:57 +080050#else
Philipp Tomsichfd1bf8d2017-06-07 18:46:00 +020051 max_frequency = dev_read_u32_default(dev, "max-frequency", 0);
Kever Yang39fbb562016-12-28 11:32:35 +080052 ret = clk_get_by_index(dev, 0, &clk);
Kever Yangc2868212017-02-13 17:38:57 +080053#endif
Kever Yang39fbb562016-12-28 11:32:35 +080054 if (!ret) {
55 ret = clk_set_rate(&clk, max_frequency);
56 if (IS_ERR_VALUE(ret))
57 printf("%s clk set rate fail!\n", __func__);
58 } else {
59 printf("%s fail to get clk\n", __func__);
60 }
Kever Yang79c83062016-07-18 17:00:58 +080061
Kever Yang79c83062016-07-18 17:00:58 +080062 host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
Stefan Herbrechtsmeier6d0e34b2017-01-17 15:58:48 +010063 host->max_clk = max_frequency;
Philipp Tomsich6837c582018-03-26 19:59:10 +020064 /*
65 * The sdhci-driver only supports 4bit and 8bit, as sdhci_setup_cfg
66 * doesn't allow us to clear MMC_MODE_4BIT. Consequently, we don't
67 * check for other bus-width values.
68 */
69 if (host->bus_width == 8)
70 host->host_caps |= MMC_MODE_8BIT;
Kever Yang79c83062016-07-18 17:00:58 +080071
Kever Yang79c83062016-07-18 17:00:58 +080072 host->mmc = &plat->mmc;
Kever Yang79c83062016-07-18 17:00:58 +080073 host->mmc->priv = &prv->host;
74 host->mmc->dev = dev;
75 upriv->mmc = host->mmc;
76
Kever Yang4dcdc5c2019-07-19 18:01:11 +080077 ret = sdhci_setup_cfg(&plat->cfg, host, 0, EMMC_MIN_FREQ);
78 if (ret)
79 return ret;
80
Kever Yang79c83062016-07-18 17:00:58 +080081 return sdhci_probe(dev);
82}
83
Simon Glassd1998a92020-12-03 16:55:21 -070084static int arasan_sdhci_of_to_plat(struct udevice *dev)
Kever Yang79c83062016-07-18 17:00:58 +080085{
Kever Yangc2868212017-02-13 17:38:57 +080086#if !CONFIG_IS_ENABLED(OF_PLATDATA)
Kever Yang79c83062016-07-18 17:00:58 +080087 struct sdhci_host *host = dev_get_priv(dev);
88
89 host->name = dev->name;
Philipp Tomsich327b2b32017-09-11 22:04:21 +020090 host->ioaddr = dev_read_addr_ptr(dev);
Philipp Tomsich6837c582018-03-26 19:59:10 +020091 host->bus_width = dev_read_u32_default(dev, "bus-width", 4);
Kever Yangc2868212017-02-13 17:38:57 +080092#endif
Kever Yang79c83062016-07-18 17:00:58 +080093
94 return 0;
95}
96
97static int rockchip_sdhci_bind(struct udevice *dev)
98{
Simon Glassc69cda22020-12-03 16:55:20 -070099 struct rockchip_sdhc_plat *plat = dev_get_plat(dev);
Kever Yang79c83062016-07-18 17:00:58 +0800100
Masahiro Yamada24f5aec2016-09-06 22:17:32 +0900101 return sdhci_bind(dev, &plat->mmc, &plat->cfg);
Kever Yang79c83062016-07-18 17:00:58 +0800102}
103
104static const struct udevice_id arasan_sdhci_ids[] = {
105 { .compatible = "arasan,sdhci-5.1" },
106 { }
107};
108
109U_BOOT_DRIVER(arasan_sdhci_drv) = {
Kever Yangc2868212017-02-13 17:38:57 +0800110 .name = "rockchip_rk3399_sdhci_5_1",
Kever Yang79c83062016-07-18 17:00:58 +0800111 .id = UCLASS_MMC,
112 .of_match = arasan_sdhci_ids,
Simon Glassd1998a92020-12-03 16:55:21 -0700113 .of_to_plat = arasan_sdhci_of_to_plat,
Kever Yang79c83062016-07-18 17:00:58 +0800114 .ops = &sdhci_ops,
115 .bind = rockchip_sdhci_bind,
116 .probe = arasan_sdhci_probe,
Simon Glass41575d82020-12-03 16:55:17 -0700117 .priv_auto = sizeof(struct rockchip_sdhc),
Simon Glasscaa4daa2020-12-03 16:55:18 -0700118 .plat_auto = sizeof(struct rockchip_sdhc_plat),
Kever Yang79c83062016-07-18 17:00:58 +0800119};