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wdenk37bd3212002-11-03 11:21:28 +00001/*------------------------------------------------------------------------------+
Josh Boyer31773492009-08-07 13:53:20 -04002 * This source code is dual-licensed. You may use it under the terms of
3 * the GNU General Public License version 2, or under the license below.
wdenk37bd3212002-11-03 11:21:28 +00004 *
5 * This source code has been made available to you by IBM on an AS-IS
6 * basis. Anyone receiving this source is licensed under IBM
7 * copyrights to use it in any way he or she deems fit, including
8 * copying it, modifying it, compiling it, and redistributing it either
9 * with or without modifications. No license under IBM patents or
10 * patent applications is to be implied by the copyright license.
11 *
12 * Any user of this software should understand that IBM cannot provide
13 * technical support for this software and will not be responsible for
14 * any consequences resulting from the use of this software.
15 *
16 * Any person who transfers this source code or any derivative work
17 * must include the IBM copyright notice, this paragraph, and the
18 * preceding two paragraphs in the transferred software.
19 *
20 * COPYRIGHT I B M CORPORATION 1995
21 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
22 *-------------------------------------------------------------------------------*/
23
24/*-----------------------------------------------------------------------------
25 * Function: ext_bus_cntlr_init
26 * Description: Initializes the External Bus Controller for the external
27 * peripherals. IMPORTANT: For pass1 this code must run from
28 * cache since you can not reliably change a peripheral banks
29 * timing register (pbxap) while running code from that bank.
30 * For ex., since we are running from ROM on bank 0, we can NOT
31 * execute the code that modifies bank 0 timings from ROM, so
32 * we run it from cache.
33 * Bank 0 - Flash or Multi Purpose Socket
34 * Bank 1 - Multi Purpose Socket or Flash (set in C-Code)
35 * Bank 2 - UART 1 (set in C-Code)
36 * Bank 3 - UART 2 (set in C-Code)
37 * Bank 4 - not used
38 * Bank 5 - not used
39 * Bank 6 - not used
40 * Bank 7 - PLD Register
41 *-----------------------------------------------------------------------------*/
42#include <ppc4xx.h>
43
44#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
45
46#include <configs/MIP405.h>
47#include <ppc_asm.tmpl>
48#include <ppc_defs.h>
49
50#include <asm/cache.h>
51#include <asm/mmu.h>
52#include "mip405.h"
53
54
wdenkf3e0de62003-06-04 15:05:30 +000055 .globl ext_bus_cntlr_init
wdenk37bd3212002-11-03 11:21:28 +000056ext_bus_cntlr_init:
wdenkf3e0de62003-06-04 15:05:30 +000057 mflr r4 /* save link register */
Stefan Roesed1c3b272009-09-09 16:25:29 +020058 mfdcr r3,CPC0_PSR /* get strapping reg */
wdenkf3e0de62003-06-04 15:05:30 +000059 andi. r0, r3, PSR_ROM_LOC /* mask out irrelevant bits */
60 bnelr /* jump back if PCI boot */
61
wdenk37bd3212002-11-03 11:21:28 +000062 bl ..getAddr
63..getAddr:
64 mflr r3 /* get address of ..getAddr */
65 mtlr r4 /* restore link register */
66 addi r4,0,14 /* set ctr to 14; used to prefetch */
67 mtctr r4 /* 14 cache lines to fit this function */
wdenk8bde7f72003-06-27 21:31:46 +000068 /* in cache (gives us 8x14=112 instrctns) */
wdenk37bd3212002-11-03 11:21:28 +000069..ebcloop:
70 icbt r0,r3 /* prefetch cache line for addr in r3 */
71 addi r3,r3,32 /* move to next cache line */
72 bdnz ..ebcloop /* continue for 14 cache lines */
73
74 /*-------------------------------------------------------------------
75 * Delay to ensure all accesses to ROM are complete before changing
76 * bank 0 timings.
77 *------------------------------------------------------------------- */
78 addis r3,0,0x0
79 ori r3,r3,0xA000
80 mtctr r3
81..spinlp:
82 bdnz ..spinlp /* spin loop */
83
84 /*-----------------------------------------------------------------------
85 * decide boot up mode
86 *----------------------------------------------------------------------- */
Stefan Roesed1c3b272009-09-09 16:25:29 +020087 addi r4,0,PB0CR
88 mtdcr EBC0_CFGADDR,r4
89 mfdcr r4,EBC0_CFGDATA
wdenk37bd3212002-11-03 11:21:28 +000090
91 andi. r0, r4, 0x2000 /* mask out irrelevant bits */
wdenk7205e402003-09-10 22:30:53 +000092 beq 0f /* jump if 8 bit bus width */
wdenk37bd3212002-11-03 11:21:28 +000093
wdenk7205e402003-09-10 22:30:53 +000094 /* setup 16 bit things
wdenk37bd3212002-11-03 11:21:28 +000095 *-----------------------------------------------------------------------
96 * Memory Bank 0 (16 Bit Flash) initialization
97 *---------------------------------------------------------------------- */
98
Stefan Roesed1c3b272009-09-09 16:25:29 +020099 addi r4,0,PB1AP
100 mtdcr EBC0_CFGADDR,r4
wdenk37bd3212002-11-03 11:21:28 +0000101 addis r4,0,(FLASH_AP_B)@h
102 ori r4,r4,(FLASH_AP_B)@l
Stefan Roesed1c3b272009-09-09 16:25:29 +0200103 mtdcr EBC0_CFGDATA,r4
wdenk37bd3212002-11-03 11:21:28 +0000104
Stefan Roesed1c3b272009-09-09 16:25:29 +0200105 addi r4,0,PB0CR
106 mtdcr EBC0_CFGADDR,r4
wdenk37bd3212002-11-03 11:21:28 +0000107 /* BS=0x010(4MB),BU=0x3(R/W), */
wdenk37bd3212002-11-03 11:21:28 +0000108 addis r4,0,(FLASH_CR_B)@h
109 ori r4,r4,(FLASH_CR_B)@l
Stefan Roesed1c3b272009-09-09 16:25:29 +0200110 mtdcr EBC0_CFGDATA,r4
wdenk37bd3212002-11-03 11:21:28 +0000111 b 1f
112
1130:
114
wdenk8bde7f72003-06-27 21:31:46 +0000115 /* 8Bit boot mode: */
wdenk37bd3212002-11-03 11:21:28 +0000116 /*-----------------------------------------------------------------------
wdenk8bde7f72003-06-27 21:31:46 +0000117 * Memory Bank 0 Multi Purpose Socket initialization
118 *----------------------------------------------------------------------- */
wdenk37bd3212002-11-03 11:21:28 +0000119 /* 0x7F8FFE80 slowest boot */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200120 addi r4,0,PB1AP
121 mtdcr EBC0_CFGADDR,r4
wdenk37bd3212002-11-03 11:21:28 +0000122 addis r4,0,(MPS_AP_B)@h
123 ori r4,r4,(MPS_AP_B)@l
Stefan Roesed1c3b272009-09-09 16:25:29 +0200124 mtdcr EBC0_CFGDATA,r4
wdenk37bd3212002-11-03 11:21:28 +0000125
Stefan Roesed1c3b272009-09-09 16:25:29 +0200126 addi r4,0,PB0CR
127 mtdcr EBC0_CFGADDR,r4
wdenk37bd3212002-11-03 11:21:28 +0000128 /* BS=0x010(4MB),BU=0x3(R/W), */
wdenk37bd3212002-11-03 11:21:28 +0000129 addis r4,0,(MPS_CR_B)@h
130 ori r4,r4,(MPS_CR_B)@l
131
Stefan Roesed1c3b272009-09-09 16:25:29 +0200132 mtdcr EBC0_CFGDATA,r4
wdenk37bd3212002-11-03 11:21:28 +0000133
134
1351:
136 /*-----------------------------------------------------------------------
137 * Memory Bank 2-3-4-5-6 (not used) initialization
138 *-----------------------------------------------------------------------*/
Stefan Roesed1c3b272009-09-09 16:25:29 +0200139 addi r4,0,PB1CR
140 mtdcr EBC0_CFGADDR,r4
wdenk37bd3212002-11-03 11:21:28 +0000141 addis r4,0,0x0000
142 ori r4,r4,0x0000
Stefan Roesed1c3b272009-09-09 16:25:29 +0200143 mtdcr EBC0_CFGDATA,r4
wdenk37bd3212002-11-03 11:21:28 +0000144
Stefan Roesed1c3b272009-09-09 16:25:29 +0200145 addi r4,0,PB2CR
146 mtdcr EBC0_CFGADDR,r4
wdenk37bd3212002-11-03 11:21:28 +0000147 addis r4,0,0x0000
148 ori r4,r4,0x0000
Stefan Roesed1c3b272009-09-09 16:25:29 +0200149 mtdcr EBC0_CFGDATA,r4
wdenk37bd3212002-11-03 11:21:28 +0000150
Stefan Roesed1c3b272009-09-09 16:25:29 +0200151 addi r4,0,PB3CR
152 mtdcr EBC0_CFGADDR,r4
wdenk37bd3212002-11-03 11:21:28 +0000153 addis r4,0,0x0000
154 ori r4,r4,0x0000
Stefan Roesed1c3b272009-09-09 16:25:29 +0200155 mtdcr EBC0_CFGDATA,r4
wdenk37bd3212002-11-03 11:21:28 +0000156
Stefan Roesed1c3b272009-09-09 16:25:29 +0200157 addi r4,0,PB4CR
158 mtdcr EBC0_CFGADDR,r4
wdenk37bd3212002-11-03 11:21:28 +0000159 addis r4,0,0x0000
160 ori r4,r4,0x0000
Stefan Roesed1c3b272009-09-09 16:25:29 +0200161 mtdcr EBC0_CFGDATA,r4
wdenk37bd3212002-11-03 11:21:28 +0000162
Stefan Roesed1c3b272009-09-09 16:25:29 +0200163 addi r4,0,PB5CR
164 mtdcr EBC0_CFGADDR,r4
wdenk37bd3212002-11-03 11:21:28 +0000165 addis r4,0,0x0000
166 ori r4,r4,0x0000
Stefan Roesed1c3b272009-09-09 16:25:29 +0200167 mtdcr EBC0_CFGDATA,r4
wdenk37bd3212002-11-03 11:21:28 +0000168
Stefan Roesed1c3b272009-09-09 16:25:29 +0200169 addi r4,0,PB6CR
170 mtdcr EBC0_CFGADDR,r4
wdenk37bd3212002-11-03 11:21:28 +0000171 addis r4,0,0x0000
172 ori r4,r4,0x0000
Stefan Roesed1c3b272009-09-09 16:25:29 +0200173 mtdcr EBC0_CFGDATA,r4
wdenk37bd3212002-11-03 11:21:28 +0000174
Stefan Roesed1c3b272009-09-09 16:25:29 +0200175 addi r4,0,PB7CR
176 mtdcr EBC0_CFGADDR,r4
wdenk37bd3212002-11-03 11:21:28 +0000177 addis r4,0,0x0000
178 ori r4,r4,0x0000
Stefan Roesed1c3b272009-09-09 16:25:29 +0200179 mtdcr EBC0_CFGDATA,r4
wdenk7205e402003-09-10 22:30:53 +0000180 nop /* pass2 DCR errata #8 */
wdenk37bd3212002-11-03 11:21:28 +0000181 blr
182
wdenkf3e0de62003-06-04 15:05:30 +0000183#if defined(CONFIG_BOOT_PCI)
184 .section .bootpg,"ax"
185 .globl _start_pci
186/*******************************************
187 */
188
189_start_pci:
190 /* first handle errata #68 / PCI_18 */
191 iccci r0, r0 /* invalidate I-cache */
192 lis r31, 0
193 mticcr r31 /* ICCR = 0 (all uncachable) */
194 isync
195
196 mfccr0 r28 /* set CCR0[24] = 1 */
197 ori r28, r28, 0x0080
198 mtccr0 r28
199
200 /* setup PMM0MA (0xEF400004) and PMM0PCIHA (0xEF40000C) */
201 lis r28, 0xEF40
202 addi r28, r28, 0x0004
203 stw r31, 0x0C(r28) /* clear PMM0PCIHA */
204 lis r29, 0xFFF8 /* open 512 kByte */
205 addi r29, r29, 0x0001/* and enable this region */
206 stwbrx r29, r0, r28 /* write PMM0MA */
207
208 lis r28, 0xEEC0 /* address of PCIC0_CFGADDR */
209 addi r29, r28, 4 /* add 4 to r29 -> PCIC0_CFGDATA */
210
211 lis r31, 0x8000 /* set en bit bus 0 */
212 ori r31, r31, 0x304C/* device 6 func 0 reg 4C (XBCS register) */
213 stwbrx r31, r0, r28 /* write it */
214
215 lwbrx r31, r0, r29 /* load XBCS register */
216 oris r31, r31, 0x02C4/* clear BIOSCS WPE, set lower, extended and 1M extended BIOS enable */
217 stwbrx r31, r0, r29 /* write back XBCS register */
218
219 nop
220 nop
221 b _start /* normal start */
222#endif