blob: c8edad867d99a31ac4e7c5229ca77f57aac621f1 [file] [log] [blame]
Yoshihiro Shimoda8e9c8972011-02-02 10:05:36 +09001/*
2 * Copyright (C) 2011 Renesas Solutions Corp.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include <common.h>
24#include <malloc.h>
25#include <asm/processor.h>
26#include <asm/io.h>
Nobuhiro Iwamatsu4f0e8472012-03-21 14:47:49 +090027#include <asm/mmc.h>
Yoshihiro Shimoda8e9c8972011-02-02 10:05:36 +090028#include <spi_flash.h>
29
30int checkboard(void)
31{
32 puts("BOARD: R0P7757LC0030RL board\n");
33
34 return 0;
35}
36
37static void init_gctrl(void)
38{
39 struct gctrl_regs *gctrl = GCTRL_BASE;
40 unsigned long graofst;
41
42 graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
43 writel(graofst | 0x20000f00, &gctrl->gracr3);
44}
45
46static int init_pcie_bridge_from_spi(void *buf, size_t size)
47{
48 struct spi_flash *spi;
49 int ret;
50 unsigned long pcie_addr;
51
52 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
53 if (!spi) {
54 printf("%s: spi_flash probe error.\n", __func__);
55 return 1;
56 }
57
58 if (is_sh7757_b0())
59 pcie_addr = SH7757LCR_PCIEBRG_ADDR_B0;
60 else
61 pcie_addr = SH7757LCR_PCIEBRG_ADDR;
62
63 ret = spi_flash_read(spi, pcie_addr, size, buf);
64 if (ret) {
65 printf("%s: spi_flash read error.\n", __func__);
66 spi_flash_free(spi);
67 return 1;
68 }
69 spi_flash_free(spi);
70
71 return 0;
72}
73
74static void init_pcie_bridge(void)
75{
76 struct pciebrg_regs *pciebrg = PCIEBRG_BASE;
77 struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
78 int i;
79 unsigned char *data;
80 unsigned short tmp;
81 unsigned long pcie_size;
82
83 if (!(readw(&pciebrg->ctrl_h8s) & 0x0001))
84 return;
85
86 if (is_sh7757_b0())
87 pcie_size = SH7757LCR_PCIEBRG_SIZE_B0;
88 else
89 pcie_size = SH7757LCR_PCIEBRG_SIZE;
90
91 data = malloc(pcie_size);
92 if (!data) {
93 printf("%s: malloc error.\n", __func__);
94 return;
95 }
96 if (init_pcie_bridge_from_spi(data, pcie_size)) {
97 free(data);
98 return;
99 }
100
101 if (data[0] == 0xff && data[1] == 0xff && data[2] == 0xff &&
102 data[3] == 0xff) {
103 free(data);
104 printf("%s: skipped initialization\n", __func__);
105 return;
106 }
107
108 writew(0xa501, &pciebrg->ctrl_h8s); /* reset */
109 writew(0x0000, &pciebrg->cp_ctrl);
110 writew(0x0000, &pciebrg->cp_addr);
111
112 for (i = 0; i < pcie_size; i += 2) {
113 tmp = (data[i] << 8) | data[i + 1];
114 writew(tmp, &pciebrg->cp_data);
115 }
116
117 writew(0xa500, &pciebrg->ctrl_h8s); /* start */
118 if (!is_sh7757_b0())
119 writel(0x00000001, &pcie_setup->pbictl3);
120
121 free(data);
122}
123
124static void init_usb_phy(void)
125{
126 struct usb_common_regs *common0 = USB0_COMMON_BASE;
127 struct usb_common_regs *common1 = USB1_COMMON_BASE;
128 struct usb0_phy_regs *phy = USB0_PHY_BASE;
129 struct usb1_port_regs *port = USB1_PORT_BASE;
130 struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
131
132 writew(0x0100, &phy->reset); /* set reset */
133 /* port0 = USB0, port1 = USB1 */
134 writew(0x0002, &phy->portsel);
135 writel(0x0001, &port->port1sel); /* port1 = Host */
136 writew(0x0111, &phy->reset); /* clear reset */
137
138 writew(0x4000, &common0->suspmode);
139 writew(0x4000, &common1->suspmode);
140
141#if defined(__LITTLE_ENDIAN)
142 writel(0x00000000, &align->ehcidatac);
143 writel(0x00000000, &align->ohcidatac);
144#endif
145}
146
147static void set_mac_to_sh_eth_register(int channel, char *mac_string)
148{
149 struct ether_mac_regs *ether;
150 unsigned char mac[6];
151 unsigned long val;
152
153 eth_parse_enetaddr(mac_string, mac);
154
155 if (!channel)
156 ether = ETHER0_MAC_BASE;
157 else
158 ether = ETHER1_MAC_BASE;
159
160 val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
161 writel(val, &ether->mahr);
162 val = (mac[4] << 8) | mac[5];
163 writel(val, &ether->malr);
164}
165
166static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
167{
168 struct ether_mac_regs *ether;
169 unsigned char mac[6];
170 unsigned long val;
171
172 eth_parse_enetaddr(mac_string, mac);
173
174 if (!channel)
175 ether = GETHER0_MAC_BASE;
176 else
177 ether = GETHER1_MAC_BASE;
178
179 val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
180 writel(val, &ether->mahr);
181 val = (mac[4] << 8) | mac[5];
182 writel(val, &ether->malr);
183}
184
185/*****************************************************************
186 * This PMB must be set on this timing. The lowlevel_init is run on
187 * Area 0(phys 0x00000000), so we have to map it.
188 *
189 * The new PMB table is following:
190 * ent virt phys v sz c wt
191 * 0 0xa0000000 0x40000000 1 128M 0 1
192 * 1 0xa8000000 0x48000000 1 128M 0 1
193 * 2 0xb0000000 0x50000000 1 128M 0 1
194 * 3 0xb8000000 0x58000000 1 128M 0 1
195 * 4 0x80000000 0x40000000 1 128M 1 1
196 * 5 0x88000000 0x48000000 1 128M 1 1
197 * 6 0x90000000 0x50000000 1 128M 1 1
198 * 7 0x98000000 0x58000000 1 128M 1 1
199 */
200static void set_pmb_on_board_init(void)
201{
202 struct mmu_regs *mmu = MMU_BASE;
203
204 /* clear ITLB */
205 writel(0x00000004, &mmu->mmucr);
206
207 /* delete PMB for SPIBOOT */
208 writel(0, PMB_ADDR_BASE(0));
209 writel(0, PMB_DATA_BASE(0));
210
211 /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
212 /* ppn ub v s1 s0 c wt */
213 writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
214 writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
215 writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
216 writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
217 writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
218 writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
219 writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
220 writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
221 writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
222 writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
223 writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
224 writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
225}
226
227int board_init(void)
228{
229 struct gether_control_regs *gether = GETHER_CONTROL_BASE;
230
231 set_pmb_on_board_init();
232
233 /* enable RMII's MDIO (disable GRMII's MDIO) */
234 writel(0x00030000, &gether->gbecont);
235
236 init_gctrl();
237 init_usb_phy();
238
239 return 0;
240}
241
242int dram_init(void)
243{
244 DECLARE_GLOBAL_DATA_PTR;
245
246 gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
247 gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
248 printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
249 printf(" Physical address\n");
250 printf(" 0x%08x - 0x%08x : Accessible Space as ECC Area\n",
251 SH7757LCR_SDRAM_PHYS_TOP,
252 SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE - 1);
253 printf(" 0x%08x - 0x%08x : No Access Area\n",
254 SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE,
255 SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE * 2 - 1);
256 printf(" 0x%08x - 0x%08x : Non-ECC Area for DVC/AVC\n",
257 SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_ECC_SETTING * 2,
258 SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_ECC_SETTING * 2 +
259 SH7757LCR_SDRAM_DVC_SIZE - 1);
260 printf(" 0x%08x - 0x%08x : Non-ECC Area for G200eR2\n",
261 SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET,
262 SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET + 0x00ffffff);
263
264 return 0;
265}
266
Yoshihiro Shimoda566f63d2012-03-05 20:11:12 +0000267int board_mmc_init(bd_t *bis)
268{
269 return mmcif_mmc_init();
270}
271
Yoshihiro Shimoda8e9c8972011-02-02 10:05:36 +0900272static int get_sh_eth_mac_raw(unsigned char *buf, int size)
273{
274 struct spi_flash *spi;
275 int ret;
276
277 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
278 if (spi == NULL) {
279 printf("%s: spi_flash probe error.\n", __func__);
280 return 1;
281 }
282
283 ret = spi_flash_read(spi, SH7757LCR_ETHERNET_MAC_BASE, size, buf);
284 if (ret) {
285 printf("%s: spi_flash read error.\n", __func__);
286 spi_flash_free(spi);
287 return 1;
288 }
289 spi_flash_free(spi);
290
291 return 0;
292}
293
294static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
295{
296 memcpy(mac_string, &buf[channel * (SH7757LCR_ETHERNET_MAC_SIZE + 1)],
297 SH7757LCR_ETHERNET_MAC_SIZE);
298 mac_string[SH7757LCR_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
299
300 return 0;
301}
302
303static void init_ethernet_mac(void)
304{
305 char mac_string[64];
306 char env_string[64];
307 int i;
308 unsigned char *buf;
309
310 buf = malloc(256);
311 if (!buf) {
312 printf("%s: malloc error.\n", __func__);
313 return;
314 }
315 get_sh_eth_mac_raw(buf, 256);
316
317 /* Fast Ethernet */
318 for (i = 0; i < SH7757LCR_ETHERNET_NUM_CH; i++) {
319 get_sh_eth_mac(i, mac_string, buf);
320 if (i == 0)
321 setenv("ethaddr", mac_string);
322 else {
323 sprintf(env_string, "eth%daddr", i);
324 setenv(env_string, mac_string);
325 }
326
327 set_mac_to_sh_eth_register(i, mac_string);
328 }
329
330 /* Gigabit Ethernet */
331 for (i = 0; i < SH7757LCR_GIGA_ETHERNET_NUM_CH; i++) {
332 get_sh_eth_mac(i + SH7757LCR_ETHERNET_NUM_CH, mac_string, buf);
333 sprintf(env_string, "eth%daddr", i + SH7757LCR_ETHERNET_NUM_CH);
334 setenv(env_string, mac_string);
335
336 set_mac_to_sh_giga_eth_register(i, mac_string);
337 }
338
339 free(buf);
340}
341
342static void init_pcie(void)
343{
344 struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
345 struct pcie_system_bus_regs *pcie_sysbus = PCIE_SYSTEM_BUS_BASE;
346
347 writel(0x00000ff2, &pcie_setup->ladmsk0);
348 writel(0x00000001, &pcie_setup->barmap);
349 writel(0xffcaa000, &pcie_setup->lad0);
350 writel(0x00030000, &pcie_sysbus->endictl0);
351 writel(0x00000003, &pcie_sysbus->endictl1);
352 writel(0x00000004, &pcie_setup->pbictl2);
353}
354
355static void finish_spiboot(void)
356{
357 struct gctrl_regs *gctrl = GCTRL_BASE;
358 /*
359 * SH7757 B0 does not use LBSC.
360 * So if we set SPIBOOTCAN to 1, SH7757 can not access Area0.
361 * This setting is not cleared by manual reset, So we have to set it
362 * to 0.
363 */
364 writel(0x00000000, &gctrl->spibootcan);
365}
366
367int board_late_init(void)
368{
369 init_ethernet_mac();
370 init_pcie_bridge();
371 init_pcie();
372 finish_spiboot();
373
374 return 0;
375}
376
377int do_sh_g200(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
378{
379 struct gctrl_regs *gctrl = GCTRL_BASE;
380 unsigned long graofst;
381
382 writel(0xfedcba98, &gctrl->wprotect);
383 graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
384 writel(graofst | 0xa0000f00, &gctrl->gracr3);
385
386 return 0;
387}
388
389U_BOOT_CMD(
390 sh_g200, 1, 1, do_sh_g200,
391 "enable sh-g200",
392 "enable SH-G200 bus (disable PCIe-G200)"
393);
394
395int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
396{
397 int i, ret;
398 char mac_string[256];
399 struct spi_flash *spi;
400 unsigned char *buf;
401
402 if (argc != 5) {
403 buf = malloc(256);
404 if (!buf) {
405 printf("%s: malloc error.\n", __func__);
406 return 1;
407 }
408
409 get_sh_eth_mac_raw(buf, 256);
410
411 /* print current MAC address */
412 for (i = 0; i < 4; i++) {
413 get_sh_eth_mac(i, mac_string, buf);
414 if (i < 2)
415 printf(" ETHERC ch%d = %s\n", i, mac_string);
416 else
417 printf("GETHERC ch%d = %s\n", i-2, mac_string);
418 }
419 free(buf);
420 return 0;
421 }
422
423 /* new setting */
424 memset(mac_string, 0xff, sizeof(mac_string));
425 sprintf(mac_string, "%s\t%s\t%s\t%s",
426 argv[1], argv[2], argv[3], argv[4]);
427
428 /* write MAC data to SPI rom */
429 spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
430 if (!spi) {
431 printf("%s: spi_flash probe error.\n", __func__);
432 return 1;
433 }
434
435 ret = spi_flash_erase(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
436 SH7757LCR_SPI_SECTOR_SIZE);
437 if (ret) {
438 printf("%s: spi_flash erase error.\n", __func__);
439 return 1;
440 }
441
442 ret = spi_flash_write(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
443 sizeof(mac_string), mac_string);
444 if (ret) {
445 printf("%s: spi_flash write error.\n", __func__);
446 spi_flash_free(spi);
447 return 1;
448 }
449 spi_flash_free(spi);
450
451 puts("The writing of the MAC address to SPI ROM was completed.\n");
452
453 return 0;
454}
455
456U_BOOT_CMD(
457 write_mac, 5, 1, do_write_mac,
458 "write MAC address for ETHERC/GETHERC",
459 "[ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1]\n"
460);