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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Gavin Guo014e4672011-11-28 20:48:14 +00002/*
3 * Faraday FTPCI100 PCI Bridge Controller Device Driver Implementation
4 *
5 * Copyright (C) 2010 Andes Technology Corporation
6 * Gavin Guo, Andes Technology Corporation <gavinguo@andestech.com>
7 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
Gavin Guo014e4672011-11-28 20:48:14 +00008 */
9
10#ifndef __FTPCI100_H
11#define __FTPCI100_H
12
13/* AHB Control Registers */
Simon Glasscd93d622020-05-10 11:40:13 -060014#include <linux/bitops.h>
Gavin Guo014e4672011-11-28 20:48:14 +000015struct ftpci100_ahbc {
16 unsigned int iosize; /* 0x00 - I/O Space Size Signal */
17 unsigned int prot; /* 0x04 - AHB Protection */
18 unsigned int rsved[8]; /* 0x08-0x24 - Reserved */
19 unsigned int conf; /* 0x28 - PCI Configuration */
20 unsigned int data; /* 0x2c - PCI Configuration DATA */
21};
22
23/*
24 * FTPCI100_IOSIZE_REG's constant definitions
25 */
26#define FTPCI100_BASE_IO_SIZE(x) (ffs(x) - 1) /* 1M - 2048M */
27
28/*
29 * PCI Configuration Register
30 */
31#define PCI_INT_MASK 0x4c
32#define PCI_MEM_BASE_SIZE1 0x50
33#define PCI_MEM_BASE_SIZE2 0x54
34#define PCI_MEM_BASE_SIZE3 0x58
35
36/*
37 * PCI_INT_MASK's bit definitions
38 */
39#define PCI_INTA_ENABLE (1 << 22)
40#define PCI_INTB_ENABLE (1 << 23)
41#define PCI_INTC_ENABLE (1 << 24)
42#define PCI_INTD_ENABLE (1 << 25)
43
44/*
45 * PCI_MEM_BASE_SIZE1's constant definitions
46 */
47#define FTPCI100_BASE_ADR_SIZE(x) ((ffs(x) - 1) << 16) /* 1M - 2048M */
48
49#define FTPCI100_MAX_FUNCTIONS 20
50#define PCI_IRQ_LINES 4
51
52#define MAX_BUS_NUM 256
53#define MAX_DEV_NUM 32
54#define MAX_FUN_NUM 8
55
56#define PCI_MAX_BAR_PER_FUNC 6
57
58/*
59 * PCI_MEM_SIZE
60 */
61#define FTPCI100_MEM_SIZE(x) (ffs(x) << 24)
62
63/* This definition is used by pci_ftpci_init() */
64#define FTPCI100_BRIDGE_VENDORID 0x159b
65#define FTPCI100_BRIDGE_DEVICEID 0x4321
66
Gabor Juhosb979cba2013-05-26 12:11:29 +020067void pci_ftpci_init(void);
68
Gavin Guo014e4672011-11-28 20:48:14 +000069struct pcibar {
70 unsigned int size;
71 unsigned int addr;
72};
73
74struct pci_config {
75 unsigned int bus;
76 unsigned int dev; /* device */
77 unsigned int func;
78 unsigned int pin;
79 unsigned short v_id; /* vendor id */
80 unsigned short d_id; /* device id */
81 struct pcibar bar[PCI_MAX_BAR_PER_FUNC + 1];
82};
83
84#endif