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Jerome Brunetdd5f2352020-03-05 12:12:38 +01001/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
Beniamino Galvanidd838402016-08-16 11:49:48 +02002/*
Beniamino Galvanidd838402016-08-16 11:49:48 +02003 * Copyright (c) 2016 BayLibre, SAS.
4 * Author: Neil Armstrong <narmstrong@baylibre.com>
Beniamino Galvanidd838402016-08-16 11:49:48 +02005 */
6#ifndef _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H
7#define _DT_BINDINGS_AMLOGIC_MESON_GXBB_RESET_H
8
9/* RESET0 */
10#define RESET_HIU 0
11/* 1 */
12#define RESET_DOS_RESET 2
13#define RESET_DDR_TOP 3
14#define RESET_DCU_RESET 4
15#define RESET_VIU 5
16#define RESET_AIU 6
17#define RESET_VID_PLL_DIV 7
18/* 8 */
19#define RESET_PMUX 9
20#define RESET_VENC 10
21#define RESET_ASSIST 11
22#define RESET_AFIFO2 12
23#define RESET_VCBUS 13
24/* 14 */
25/* 15 */
26#define RESET_GIC 16
27#define RESET_CAPB3_DECODE 17
28#define RESET_NAND_CAPB3 18
29#define RESET_HDMITX_CAPB3 19
30#define RESET_MALI_CAPB3 20
31#define RESET_DOS_CAPB3 21
32#define RESET_SYS_CPU_CAPB3 22
33#define RESET_CBUS_CAPB3 23
34#define RESET_AHB_CNTL 24
35#define RESET_AHB_DATA 25
36#define RESET_VCBUS_CLK81 26
37#define RESET_MMC 27
38#define RESET_MIPI_0 28
39#define RESET_MIPI_1 29
40#define RESET_MIPI_2 30
41#define RESET_MIPI_3 31
42/* RESET1 */
43#define RESET_CPPM 32
44#define RESET_DEMUX 33
45#define RESET_USB_OTG 34
46#define RESET_DDR 35
47#define RESET_AO_RESET 36
48#define RESET_BT656 37
49#define RESET_AHB_SRAM 38
50/* 39 */
51#define RESET_PARSER 40
52#define RESET_BLKMV 41
53#define RESET_ISA 42
54#define RESET_ETHERNET 43
55#define RESET_SD_EMMC_A 44
56#define RESET_SD_EMMC_B 45
57#define RESET_SD_EMMC_C 46
58#define RESET_ROM_BOOT 47
59#define RESET_SYS_CPU_0 48
60#define RESET_SYS_CPU_1 49
61#define RESET_SYS_CPU_2 50
62#define RESET_SYS_CPU_3 51
63#define RESET_SYS_CPU_CORE_0 52
64#define RESET_SYS_CPU_CORE_1 53
65#define RESET_SYS_CPU_CORE_2 54
66#define RESET_SYS_CPU_CORE_3 55
67#define RESET_SYS_PLL_DIV 56
68#define RESET_SYS_CPU_AXI 57
69#define RESET_SYS_CPU_L2 58
70#define RESET_SYS_CPU_P 59
71#define RESET_SYS_CPU_MBIST 60
Neil Armstrong4e7b0a32020-09-10 10:48:12 +020072#define RESET_ACODEC 61
Beniamino Galvanidd838402016-08-16 11:49:48 +020073/* 62 */
74/* 63 */
75/* RESET2 */
76#define RESET_VD_RMEM 64
77#define RESET_AUDIN 65
78#define RESET_HDMI_TX 66
79/* 67 */
80/* 68 */
81/* 69 */
82#define RESET_GE2D 70
83#define RESET_PARSER_REG 71
84#define RESET_PARSER_FETCH 72
85#define RESET_PARSER_CTL 73
86#define RESET_PARSER_TOP 74
87/* 75 */
88/* 76 */
89#define RESET_AO_CPU_RESET 77
90#define RESET_MALI 78
91#define RESET_HDMI_SYSTEM_RESET 79
92/* 80-95 */
93/* RESET3 */
94#define RESET_RING_OSCILLATOR 96
95#define RESET_SYS_CPU 97
96#define RESET_EFUSE 98
97#define RESET_SYS_CPU_BVCI 99
98#define RESET_AIFIFO 100
99#define RESET_TVFE 101
100#define RESET_AHB_BRIDGE_CNTL 102
101/* 103 */
102#define RESET_AUDIO_DAC 104
103#define RESET_DEMUX_TOP 105
104#define RESET_DEMUX_DES 106
105#define RESET_DEMUX_S2P_0 107
106#define RESET_DEMUX_S2P_1 108
107#define RESET_DEMUX_RESET_0 109
108#define RESET_DEMUX_RESET_1 110
109#define RESET_DEMUX_RESET_2 111
110/* 112-127 */
111/* RESET4 */
112/* 128 */
113/* 129 */
114/* 130 */
115/* 131 */
116#define RESET_DVIN_RESET 132
117#define RESET_RDMA 133
118#define RESET_VENCI 134
119#define RESET_VENCP 135
120/* 136 */
121#define RESET_VDAC 137
122#define RESET_RTC 138
123/* 139 */
124#define RESET_VDI6 140
125#define RESET_VENCL 141
126#define RESET_I2C_MASTER_2 142
127#define RESET_I2C_MASTER_1 143
128/* 144-159 */
129/* RESET5 */
130/* 160-191 */
131/* RESET6 */
132#define RESET_PERIPHS_GENERAL 192
133#define RESET_PERIPHS_SPICC 193
134#define RESET_PERIPHS_SMART_CARD 194
135#define RESET_PERIPHS_SAR_ADC 195
136#define RESET_PERIPHS_I2C_MASTER_0 196
137#define RESET_SANA 197
138/* 198 */
139#define RESET_PERIPHS_STREAM_INTERFACE 199
140#define RESET_PERIPHS_SDIO 200
141#define RESET_PERIPHS_UART_0 201
142#define RESET_PERIPHS_UART_1_2 202
143#define RESET_PERIPHS_ASYNC_0 203
144#define RESET_PERIPHS_ASYNC_1 204
145#define RESET_PERIPHS_SPI_0 205
146#define RESET_PERIPHS_SDHC 206
147#define RESET_UART_SLIP 207
148/* 208-223 */
149/* RESET7 */
150#define RESET_USB_DDR_0 224
151#define RESET_USB_DDR_1 225
152#define RESET_USB_DDR_2 226
153#define RESET_USB_DDR_3 227
154/* 228 */
155#define RESET_DEVICE_MMC_ARB 229
156/* 230 */
157#define RESET_VID_LOCK 231
158#define RESET_A9_DMC_PIPEL 232
159/* 233-255 */
160
161#endif