| Sagar Shrikant Kadam | ef9f65f | 2020-07-29 02:36:10 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (C) 2020 Sifive, Inc. |
| 4 | * Author: Sagar Kadam <sagar.kadam@sifive.com> |
| 5 | */ |
| 6 | |
| 7 | #ifndef __DT_BINDINGS_RESET_SIFIVE_FU540_PRCI_H |
| 8 | #define __DT_BINDINGS_RESET_SIFIVE_FU540_PRCI_H |
| 9 | |
| 10 | /* Reset indexes for use by device tree data and the PRCI driver */ |
| 11 | #define PRCI_RST_DDR_CTRL_N 0 |
| 12 | #define PRCI_RST_DDR_AXI_N 1 |
| 13 | #define PRCI_RST_DDR_AHB_N 2 |
| 14 | #define PRCI_RST_DDR_PHY_N 3 |
| 15 | /* bit 4 is reserved bit */ |
| 16 | #define PRCI_RST_RSVD_N 4 |
| 17 | #define PRCI_RST_GEMGXL_N 5 |
| 18 | |
| 19 | #endif |