Hannes Schmelzer | c04ac5b | 2019-07-17 14:29:53 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Config file for BuR BRPP2_IMX6 board |
| 4 | * |
| 5 | * Copyright (C) 2018 |
| 6 | * B&R Industrial Automation GmbH - http://www.br-automation.com/ |
| 7 | */ |
| 8 | #ifndef __CONFIG_BRPP2_IMX6_H |
| 9 | #define __CONFIG_BRPP2_IMX6_H |
| 10 | |
| 11 | #include <configs/bur_cfg_common.h> |
| 12 | #include <asm/arch/imx-regs.h> |
| 13 | |
| 14 | /* -- i.mx6 specifica -- */ |
| 15 | #ifndef CONFIG_SYS_L2CACHE_OFF |
| 16 | #define CONFIG_SYS_L2_PL310 |
| 17 | #define CONFIG_SYS_PL310_BASE L2_PL310_BASE |
| 18 | #endif /* !CONFIG_SYS_L2CACHE_OFF */ |
| 19 | |
| 20 | #define CONFIG_BOARD_POSTCLK_INIT |
| 21 | #define CONFIG_MXC_GPT_HCLK |
| 22 | |
| 23 | #define CONFIG_LOADADDR 0x10700000 |
| 24 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
| 25 | |
| 26 | /* MMC */ |
| 27 | #define CONFIG_FSL_USDHC |
| 28 | |
| 29 | /* Boot */ |
| 30 | #define CONFIG_CMDLINE_TAG |
| 31 | #define CONFIG_SETUP_MEMORY_TAGS |
| 32 | #define CONFIG_INITRD_TAG |
| 33 | #define CONFIG_MACH_TYPE 0xFFFFFFFF |
| 34 | |
| 35 | /* misc */ |
| 36 | #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) |
| 37 | |
| 38 | /* Environment */ |
| 39 | #define CONFIG_ENV_OVERWRITE |
| 40 | #define CONFIG_ENV_SECT_SIZE 0x10000 |
| 41 | #define CONFIG_ENV_SIZE 0x10000 |
| 42 | #define CONFIG_ENV_OFFSET 0x20000 |
| 43 | |
| 44 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 45 | BUR_COMMON_ENV \ |
| 46 | "autoload=0\0" \ |
| 47 | "cfgaddr=0x106F0000\0" \ |
| 48 | "scraddr=0x10700000\0" \ |
| 49 | "loadaddr=0x10800000\0" \ |
| 50 | "dtbaddr=0x12000000\0" \ |
| 51 | "ramaddr=0x12100000\0" \ |
| 52 | "cfgscr=mw ${loadaddr} 0 128\0" \ |
| 53 | "cfgscrl=fdt addr ${dtbaddr} &&"\ |
| 54 | " sf probe; sf read ${cfgaddr} 0x40000 0x10000 && source ${cfgaddr}\0" \ |
| 55 | "console=ttymxc0,115200n8 consoleblank=0 quiet\0" \ |
| 56 | "t50args#0=setenv bootargs b_mode=${b_mode} console=${console} " \ |
| 57 | " root=/dev/mmcblk0p2 rootfstype=ext4 rootwait panic=2 \0" \ |
| 58 | "b_t50lgcy#0=" \ |
| 59 | "load ${loaddev}:2 ${loadaddr} /boot/zImage && " \ |
| 60 | "load ${loaddev}:2 ${dtbaddr} /boot/imx6dl-brppt50.dtb; " \ |
| 61 | "run t50args#0; run cfgscrl; bootz ${loadaddr} - ${dtbaddr}\0" \ |
| 62 | "t50args#1=setenv bootargs console=${console} b_mode=${b_mode}" \ |
| 63 | " rootwait panic=2\0" \ |
| 64 | "b_t50lgcy#1=" \ |
| 65 | "load ${loaddev}:1 ${loadaddr} zImage && " \ |
| 66 | "load ${loaddev}:1 ${dtbaddr} imx6dl-brppt50.dtb && " \ |
| 67 | "load ${loaddev}:1 ${ramaddr} rootfsPPT50.uboot && " \ |
| 68 | "run t50args#1; run cfgscrl; bootz ${loadaddr} ${ramaddr} ${dtbaddr}\0"\ |
| 69 | "b_mmc0=load ${loaddev}:1 ${scraddr} bootscr.img && source ${scraddr}\0" \ |
| 70 | "b_mmc1=load ${loaddev}:1 ${scraddr} /boot/bootscr.img && source ${scraddr}\0" \ |
| 71 | "b_usb0=usb start && load usb 0 ${scraddr} bootscr.img && source ${scraddr}\0" \ |
| 72 | "b_net=tftp ${scraddr} netscript.img && source ${scraddr}\0" \ |
| 73 | "b_tgts_std=mmc0 mmc1 t50lgcy#0 t50lgcy#1 usb0 net\0" \ |
| 74 | "b_tgts_rcy=t50lgcy#1 usb0 net\0" \ |
| 75 | "b_tgts_pme=net usb0 mmc0 mmc1\0" \ |
| 76 | "b_mode=4\0" \ |
| 77 | "b_break=0\0" \ |
| 78 | "b_deftgts=if test ${b_mode} = 12; then setenv b_tgts ${b_tgts_pme};" \ |
| 79 | " elif test ${b_mode} = 0; then setenv b_tgts ${b_tgts_rcy};" \ |
| 80 | " else setenv b_tgts ${b_tgts_std}; fi\0" \ |
| 81 | "b_default=run b_deftgts; for target in ${b_tgts};"\ |
| 82 | " do echo \"### booting ${target} ###\"; run b_${target};" \ |
| 83 | " if test ${b_break} = 1; then; exit; fi; done\0" \ |
| 84 | "loaddev=mmc 0\0" \ |
| 85 | "altbootcmd=setenv b_mode 0; run b_default;\0" \ |
| 86 | "bootlimit=1\0" \ |
| 87 | "net2nor=sf probe && dhcp &&" \ |
| 88 | " tftp ${loadaddr} SPL && sf erase 0 +${filesize} &&" \ |
| 89 | " sf write ${loadaddr} 400 ${filesize} &&" \ |
| 90 | " tftp ${loadaddr} u-boot-dtb.img && sf erase 0x100000 +${filesize} &&" \ |
| 91 | " sf write ${loadaddr} 0x100000 ${filesize}\0" |
| 92 | |
| 93 | /* RAM */ |
| 94 | #define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR |
| 95 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
| 96 | #define CONFIG_SYS_MEMTEST_START 0x10000000 |
| 97 | #define CONFIG_SYS_MEMTEST_END 0x10010000 |
| 98 | #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR |
| 99 | #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE |
| 100 | #define CONFIG_SYS_INIT_SP_OFFSET \ |
| 101 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
| 102 | #define CONFIG_SYS_INIT_SP_ADDR \ |
| 103 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) |
| 104 | |
| 105 | /* Ethernet */ |
| 106 | #define CONFIG_MII |
| 107 | #define CONFIG_FEC_XCV_TYPE RGMII |
| 108 | #define CONFIG_FEC_FIXED_SPEED _1000BASET |
| 109 | #define CONFIG_ARP_TIMEOUT 1500UL |
| 110 | |
| 111 | /* USB Configs */ |
| 112 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
| 113 | #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) |
| 114 | |
| 115 | /* SPL */ |
| 116 | #ifdef CONFIG_SPL |
| 117 | #include "imx6_spl.h" |
| 118 | |
| 119 | #endif /* CONFIG_SPL */ |
| 120 | #endif /* __CONFIG_BRPP2_IMX6_H */ |