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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0 */
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +09002/*
3 * R8A66597 HCD (Host Controller Driver) for u-boot
4 *
5 * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +09006 */
7
8#ifndef __R8A66597_H__
9#define __R8A66597_H__
10
11#define SYSCFG0 0x00
12#define SYSCFG1 0x02
13#define SYSSTS0 0x04
14#define SYSSTS1 0x06
15#define DVSTCTR0 0x08
16#define DVSTCTR1 0x0A
17#define TESTMODE 0x0C
18#define PINCFG 0x0E
19#define DMA0CFG 0x10
20#define DMA1CFG 0x12
21#define CFIFO 0x14
22#define D0FIFO 0x18
23#define D1FIFO 0x1C
24#define CFIFOSEL 0x20
25#define CFIFOCTR 0x22
26#define CFIFOSIE 0x24
27#define D0FIFOSEL 0x28
28#define D0FIFOCTR 0x2A
29#define D1FIFOSEL 0x2C
30#define D1FIFOCTR 0x2E
31#define INTENB0 0x30
32#define INTENB1 0x32
33#define INTENB2 0x34
34#define BRDYENB 0x36
35#define NRDYENB 0x38
36#define BEMPENB 0x3A
37#define SOFCFG 0x3C
38#define INTSTS0 0x40
39#define INTSTS1 0x42
40#define INTSTS2 0x44
41#define BRDYSTS 0x46
42#define NRDYSTS 0x48
43#define BEMPSTS 0x4A
44#define FRMNUM 0x4C
45#define UFRMNUM 0x4E
46#define USBADDR 0x50
47#define USBREQ 0x54
48#define USBVAL 0x56
49#define USBINDX 0x58
50#define USBLENG 0x5A
51#define DCPCFG 0x5C
52#define DCPMAXP 0x5E
53#define DCPCTR 0x60
54#define PIPESEL 0x64
55#define PIPECFG 0x68
56#define PIPEBUF 0x6A
57#define PIPEMAXP 0x6C
58#define PIPEPERI 0x6E
59#define PIPE1CTR 0x70
60#define PIPE2CTR 0x72
61#define PIPE3CTR 0x74
62#define PIPE4CTR 0x76
63#define PIPE5CTR 0x78
64#define PIPE6CTR 0x7A
65#define PIPE7CTR 0x7C
66#define PIPE8CTR 0x7E
67#define PIPE9CTR 0x80
68#define PIPE1TRE 0x90
69#define PIPE1TRN 0x92
70#define PIPE2TRE 0x94
71#define PIPE2TRN 0x96
72#define PIPE3TRE 0x98
73#define PIPE3TRN 0x9A
74#define PIPE4TRE 0x9C
Marek Vasut8b548302019-08-11 13:44:10 +020075#define PIPE4TRN 0x9E
76#define PIPE5TRE 0xA0
77#define PIPE5TRN 0xA2
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +090078#define DEVADD0 0xD0
79#define DEVADD1 0xD2
80#define DEVADD2 0xD4
81#define DEVADD3 0xD6
82#define DEVADD4 0xD8
83#define DEVADD5 0xDA
84#define DEVADD6 0xDC
85#define DEVADD7 0xDE
86#define DEVADD8 0xE0
87#define DEVADD9 0xE2
88#define DEVADDA 0xE4
Chris Brandt11f46782017-11-27 14:04:10 -050089#define SUSPMODE0 0x102 /* RZ/A only */
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +090090
91/* System Configuration Control Register */
Marek Vasut8b548302019-08-11 13:44:10 +020092#define HSE 0x0080 /* b7: Hi-speed enable */
93#define DCFM 0x0040 /* b6: Controller function select */
94#define DRPD 0x0020 /* b5: D+/- pull down control */
95#define DPRPU 0x0010 /* b4: D+ pull up control */
96#define XTAL 0x0004 /* b2: Crystal selection */
97#define XTAL12 0x0004 /* 12MHz */
98#define XTAL48 0x0000 /* 48MHz */
99#define UPLLE 0x0002 /* b1: internal PLL control */
100#define USBE 0x0001 /* b0: USB module operation enable */
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900101
102/* System Configuration Status Register */
Marek Vasut8b548302019-08-11 13:44:10 +0200103#define OVCBIT 0x8000 /* b15-14: Over-current bit */
104#define OVCMON 0xC000 /* b15-14: Over-current monitor */
105#define SOFEA 0x0020 /* b5: SOF monitor */
106#define IDMON 0x0004 /* b3: ID-pin monitor */
107#define LNST 0x0003 /* b1-0: D+, D- line status */
108#define SE1 0x0003 /* SE1 */
109#define FS_KSTS 0x0002 /* Full-Speed K State */
110#define FS_JSTS 0x0001 /* Full-Speed J State */
111#define LS_JSTS 0x0002 /* Low-Speed J State */
112#define LS_KSTS 0x0001 /* Low-Speed K State */
113#define SE0 0x0000 /* SE0 */
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900114
115/* Device State Control Register */
Marek Vasut8b548302019-08-11 13:44:10 +0200116#define EXTLP0 0x0400 /* b10: External port */
117#define VBOUT 0x0200 /* b9: VBUS output */
118#define WKUP 0x0100 /* b8: Remote wakeup */
119#define RWUPE 0x0080 /* b7: Remote wakeup sense */
120#define USBRST 0x0040 /* b6: USB reset enable */
121#define RESUME 0x0020 /* b5: Resume enable */
122#define UACT 0x0010 /* b4: USB bus enable */
123#define RHST 0x0007 /* b1-0: Reset handshake status */
124#define HSPROC 0x0004 /* HS handshake is processing */
125#define HSMODE 0x0003 /* Hi-Speed mode */
126#define FSMODE 0x0002 /* Full-Speed mode */
127#define LSMODE 0x0001 /* Low-Speed mode */
128#define UNDECID 0x0000 /* Undecided */
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900129
130/* Test Mode Register */
Marek Vasut8b548302019-08-11 13:44:10 +0200131#define UTST 0x000F /* b3-0: Test select */
132#define H_TST_PACKET 0x000C /* HOST TEST Packet */
133#define H_TST_SE0_NAK 0x000B /* HOST TEST SE0 NAK */
134#define H_TST_K 0x000A /* HOST TEST K */
135#define H_TST_J 0x0009 /* HOST TEST J */
136#define H_TST_NORMAL 0x0000 /* HOST Normal Mode */
137#define P_TST_PACKET 0x0004 /* PERI TEST Packet */
138#define P_TST_SE0_NAK 0x0003 /* PERI TEST SE0 NAK */
139#define P_TST_K 0x0002 /* PERI TEST K */
140#define P_TST_J 0x0001 /* PERI TEST J */
141#define P_TST_NORMAL 0x0000 /* PERI Normal Mode */
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900142
143/* Data Pin Configuration Register */
Marek Vasut8b548302019-08-11 13:44:10 +0200144#define LDRV 0x8000 /* b15: Drive Current Adjust */
145#define VIF1 0x0000 /* VIF = 1.8V */
146#define VIF3 0x8000 /* VIF = 3.3V */
147#define INTA 0x0001 /* b1: USB INT-pin active */
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900148
149/* DMAx Pin Configuration Register */
Marek Vasut8b548302019-08-11 13:44:10 +0200150#define DREQA 0x4000 /* b14: Dreq active select */
151#define BURST 0x2000 /* b13: Burst mode */
152#define DACKA 0x0400 /* b10: Dack active select */
153#define DFORM 0x0380 /* b9-7: DMA mode select */
154#define CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */
155#define CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */
156#define CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */
157#define SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */
158#define DENDA 0x0040 /* b6: Dend active select */
159#define PKTM 0x0020 /* b5: Packet mode */
160#define DENDE 0x0010 /* b4: Dend enable */
161#define OBUS 0x0004 /* b2: OUTbus mode */
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900162
163/* CFIFO/DxFIFO Port Select Register */
Marek Vasut8b548302019-08-11 13:44:10 +0200164#define RCNT 0x8000 /* b15: Read count mode */
165#define REW 0x4000 /* b14: Buffer rewind */
166#define DCLRM 0x2000 /* b13: DMA buffer clear mode */
167#define DREQE 0x1000 /* b12: DREQ output enable */
168#define MBW 0x0800 /* b10: Maximum bit width for FIFO access */
169#define MBW_8 0x0000 /* 8bit */
170#define MBW_16 0x0400 /* 16bit */
171#define MBW_32 0x0800 /* 32bit */
172#define BIGEND 0x0100 /* b8: Big endian mode */
173#define BYTE_LITTLE 0x0000 /* little dendian */
174#define BYTE_BIG 0x0100 /* big endifan */
175#define ISEL 0x0020 /* b5: DCP FIFO port direction select */
176#define CURPIPE 0x000F /* b2-0: PIPE select */
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900177
178/* CFIFO/DxFIFO Port Control Register */
Marek Vasut8b548302019-08-11 13:44:10 +0200179#define BVAL 0x8000 /* b15: Buffer valid flag */
180#define BCLR 0x4000 /* b14: Buffer clear */
181#define FRDY 0x2000 /* b13: FIFO ready */
182#define DTLN 0x0FFF /* b11-0: FIFO received data length */
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900183
184/* Interrupt Enable Register 0 */
Marek Vasut8b548302019-08-11 13:44:10 +0200185#define VBSE 0x8000 /* b15: VBUS interrupt */
186#define RSME 0x4000 /* b14: Resume interrupt */
187#define SOFE 0x2000 /* b13: Frame update interrupt */
188#define DVSE 0x1000 /* b12: Device state transition interrupt */
189#define CTRE 0x0800 /* b11: Control transfer stage transition interrupt */
190#define BEMPE 0x0400 /* b10: Buffer empty interrupt */
191#define NRDYE 0x0200 /* b9: Buffer not ready interrupt */
192#define BRDYE 0x0100 /* b8: Buffer ready interrupt */
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900193
194/* Interrupt Enable Register 1 */
Marek Vasut8b548302019-08-11 13:44:10 +0200195#define OVRCRE 0x8000 /* b15: Over-current interrupt */
196#define BCHGE 0x4000 /* b14: USB us chenge interrupt */
197#define DTCHE 0x1000 /* b12: Detach sense interrupt */
198#define ATTCHE 0x0800 /* b11: Attach sense interrupt */
199#define EOFERRE 0x0040 /* b6: EOF error interrupt */
200#define SIGNE 0x0020 /* b5: SETUP IGNORE interrupt */
201#define SACKE 0x0010 /* b4: SETUP ACK interrupt */
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900202
203/* BRDY Interrupt Enable/Status Register */
Marek Vasut8b548302019-08-11 13:44:10 +0200204#define BRDY9 0x0200 /* b9: PIPE9 */
205#define BRDY8 0x0100 /* b8: PIPE8 */
206#define BRDY7 0x0080 /* b7: PIPE7 */
207#define BRDY6 0x0040 /* b6: PIPE6 */
208#define BRDY5 0x0020 /* b5: PIPE5 */
209#define BRDY4 0x0010 /* b4: PIPE4 */
210#define BRDY3 0x0008 /* b3: PIPE3 */
211#define BRDY2 0x0004 /* b2: PIPE2 */
212#define BRDY1 0x0002 /* b1: PIPE1 */
213#define BRDY0 0x0001 /* b1: PIPE0 */
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900214
215/* NRDY Interrupt Enable/Status Register */
Marek Vasut8b548302019-08-11 13:44:10 +0200216#define NRDY9 0x0200 /* b9: PIPE9 */
217#define NRDY8 0x0100 /* b8: PIPE8 */
218#define NRDY7 0x0080 /* b7: PIPE7 */
219#define NRDY6 0x0040 /* b6: PIPE6 */
220#define NRDY5 0x0020 /* b5: PIPE5 */
221#define NRDY4 0x0010 /* b4: PIPE4 */
222#define NRDY3 0x0008 /* b3: PIPE3 */
223#define NRDY2 0x0004 /* b2: PIPE2 */
224#define NRDY1 0x0002 /* b1: PIPE1 */
225#define NRDY0 0x0001 /* b1: PIPE0 */
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900226
227/* BEMP Interrupt Enable/Status Register */
Marek Vasut8b548302019-08-11 13:44:10 +0200228#define BEMP9 0x0200 /* b9: PIPE9 */
229#define BEMP8 0x0100 /* b8: PIPE8 */
230#define BEMP7 0x0080 /* b7: PIPE7 */
231#define BEMP6 0x0040 /* b6: PIPE6 */
232#define BEMP5 0x0020 /* b5: PIPE5 */
233#define BEMP4 0x0010 /* b4: PIPE4 */
234#define BEMP3 0x0008 /* b3: PIPE3 */
235#define BEMP2 0x0004 /* b2: PIPE2 */
236#define BEMP1 0x0002 /* b1: PIPE1 */
237#define BEMP0 0x0001 /* b0: PIPE0 */
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900238
239/* SOF Pin Configuration Register */
Marek Vasut8b548302019-08-11 13:44:10 +0200240#define TRNENSEL 0x0100 /* b8: Select transaction enable period */
241#define BRDYM 0x0040 /* b6: BRDY clear timing */
242#define INTL 0x0020 /* b5: Interrupt sense select */
243#define EDGESTS 0x0010 /* b4: */
244#define SOFMODE 0x000C /* b3-2: SOF pin select */
245#define SOF_125US 0x0008 /* SOF OUT 125us Frame Signal */
246#define SOF_1MS 0x0004 /* SOF OUT 1ms Frame Signal */
247#define SOF_DISABLE 0x0000 /* SOF OUT Disable */
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900248
249/* Interrupt Status Register 0 */
Marek Vasut8b548302019-08-11 13:44:10 +0200250#define VBINT 0x8000 /* b15: VBUS interrupt */
251#define RESM 0x4000 /* b14: Resume interrupt */
252#define SOFR 0x2000 /* b13: SOF frame update interrupt */
253#define DVST 0x1000 /* b12: Device state transition interrupt */
254#define CTRT 0x0800 /* b11: Control transfer stage transition interrupt */
255#define BEMP 0x0400 /* b10: Buffer empty interrupt */
256#define NRDY 0x0200 /* b9: Buffer not ready interrupt */
257#define BRDY 0x0100 /* b8: Buffer ready interrupt */
258#define VBSTS 0x0080 /* b7: VBUS input port */
259#define DVSQ 0x0070 /* b6-4: Device state */
260#define DS_SPD_CNFG 0x0070 /* Suspend Configured */
261#define DS_SPD_ADDR 0x0060 /* Suspend Address */
262#define DS_SPD_DFLT 0x0050 /* Suspend Default */
263#define DS_SPD_POWR 0x0040 /* Suspend Powered */
264#define DS_SUSP 0x0040 /* Suspend */
265#define DS_CNFG 0x0030 /* Configured */
266#define DS_ADDS 0x0020 /* Address */
267#define DS_DFLT 0x0010 /* Default */
268#define DS_POWR 0x0000 /* Powered */
269#define DVSQS 0x0030 /* b5-4: Device state */
270#define VALID 0x0008 /* b3: Setup packet detected flag */
271#define CTSQ 0x0007 /* b2-0: Control transfer stage */
272#define CS_SQER 0x0006 /* Sequence error */
273#define CS_WRND 0x0005 /* Control write nodata status stage */
274#define CS_WRSS 0x0004 /* Control write status stage */
275#define CS_WRDS 0x0003 /* Control write data stage */
276#define CS_RDSS 0x0002 /* Control read status stage */
277#define CS_RDDS 0x0001 /* Control read data stage */
278#define CS_IDST 0x0000 /* Idle or setup stage */
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900279
280/* Interrupt Status Register 1 */
Marek Vasut8b548302019-08-11 13:44:10 +0200281#define OVRCR 0x8000 /* b15: Over-current interrupt */
282#define BCHG 0x4000 /* b14: USB bus chenge interrupt */
283#define DTCH 0x1000 /* b12: Detach sense interrupt */
284#define ATTCH 0x0800 /* b11: Attach sense interrupt */
285#define EOFERR 0x0040 /* b6: EOF-error interrupt */
286#define SIGN 0x0020 /* b5: Setup ignore interrupt */
287#define SACK 0x0010 /* b4: Setup acknowledge interrupt */
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900288
289/* Frame Number Register */
Marek Vasut8b548302019-08-11 13:44:10 +0200290#define OVRN 0x8000 /* b15: Overrun error */
291#define CRCE 0x4000 /* b14: Received data error */
292#define FRNM 0x07FF /* b10-0: Frame number */
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900293
294/* Micro Frame Number Register */
Marek Vasut8b548302019-08-11 13:44:10 +0200295#define UFRNM 0x0007 /* b2-0: Micro frame number */
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900296
297/* Default Control Pipe Maxpacket Size Register */
298/* Pipe Maxpacket Size Register */
Marek Vasut8b548302019-08-11 13:44:10 +0200299#define DEVSEL 0xF000 /* b15-14: Device address select */
300#define MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900301
302/* Default Control Pipe Control Register */
Marek Vasut8b548302019-08-11 13:44:10 +0200303#define BSTS 0x8000 /* b15: Buffer status */
304#define SUREQ 0x4000 /* b14: Send USB request */
305#define CSCLR 0x2000 /* b13: complete-split status clear */
306#define CSSTS 0x1000 /* b12: complete-split status */
307#define SUREQCLR 0x0800 /* b11: stop setup request */
308#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
309#define SQSET 0x0080 /* b7: Sequence toggle bit set */
310#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
311#define PBUSY 0x0020 /* b5: pipe busy */
312#define PINGE 0x0010 /* b4: ping enable */
313#define CCPL 0x0004 /* b2: Enable control transfer complete */
314#define PID 0x0003 /* b1-0: Response PID */
315#define PID_STALL11 0x0003 /* STALL */
316#define PID_STALL 0x0002 /* STALL */
317#define PID_BUF 0x0001 /* BUF */
318#define PID_NAK 0x0000 /* NAK */
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900319
320/* Pipe Window Select Register */
Marek Vasut8b548302019-08-11 13:44:10 +0200321#define PIPENM 0x0007 /* b2-0: Pipe select */
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900322
323/* Pipe Configuration Register */
Marek Vasut8b548302019-08-11 13:44:10 +0200324#define R8A66597_TYP 0xC000 /* b15-14: Transfer type */
325#define R8A66597_ISO 0xC000 /* Isochronous */
326#define R8A66597_INT 0x8000 /* Interrupt */
327#define R8A66597_BULK 0x4000 /* Bulk */
328#define R8A66597_BFRE 0x0400 /* b10: Buffer ready interrupt mode select */
329#define R8A66597_DBLB 0x0200 /* b9: Double buffer mode select */
330#define R8A66597_CNTMD 0x0100 /* b8: Continuous transfer mode select */
331#define R8A66597_SHTNAK 0x0080 /* b7: Transfer end NAK */
332#define R8A66597_DIR 0x0010 /* b4: Transfer direction select */
333#define R8A66597_EPNUM 0x000F /* b3-0: Eendpoint number select */
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900334
335/* Pipe Buffer Configuration Register */
Marek Vasut8b548302019-08-11 13:44:10 +0200336#define BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */
337#define BUFNMB 0x007F /* b6-0: Pipe buffer number */
338#define PIPE0BUF 256
339#define PIPExBUF 64
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900340
341/* Pipe Maxpacket Size Register */
Marek Vasut8b548302019-08-11 13:44:10 +0200342#define MXPS 0x07FF /* b10-0: Maxpacket size */
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900343
344/* Pipe Cycle Configuration Register */
Marek Vasut8b548302019-08-11 13:44:10 +0200345#define IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */
346#define IITV 0x0007 /* b2-0: Isochronous interval */
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900347
348/* Pipex Control Register */
Marek Vasut8b548302019-08-11 13:44:10 +0200349#define BSTS 0x8000 /* b15: Buffer status */
350#define INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */
351#define CSCLR 0x2000 /* b13: complete-split status clear */
352#define CSSTS 0x1000 /* b12: complete-split status */
353#define ATREPM 0x0400 /* b10: Auto repeat mode */
354#define ACLRM 0x0200 /* b9: Out buffer auto clear mode */
355#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
356#define SQSET 0x0080 /* b7: Sequence toggle bit set */
357#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
358#define PBUSY 0x0020 /* b5: pipe busy */
359#define PID 0x0003 /* b1-0: Response PID */
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900360
361/* PIPExTRE */
Marek Vasut8b548302019-08-11 13:44:10 +0200362#define TRENB 0x0200 /* b9: Transaction counter enable */
363#define TRCLR 0x0100 /* b8: Transaction counter clear */
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900364
365/* PIPExTRN */
Marek Vasut8b548302019-08-11 13:44:10 +0200366#define TRNCNT 0xFFFF /* b15-0: Transaction counter */
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900367
368/* DEVADDx */
Marek Vasut8b548302019-08-11 13:44:10 +0200369#define UPPHUB 0x7800
370#define HUBPORT 0x0700
371#define USBSPD 0x00C0
372#define RTPORT 0x0001
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900373
Chris Brandt11f46782017-11-27 14:04:10 -0500374/* Suspend Mode Register */
Marek Vasut8b548302019-08-11 13:44:10 +0200375#define SUSPM 0x4000 /* b14: Suspend */
Chris Brandt11f46782017-11-27 14:04:10 -0500376
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900377#define R8A66597_MAX_NUM_PIPE 10
378#define R8A66597_BUF_BSIZE 8
379#define R8A66597_MAX_DEVICE 10
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900380#define R8A66597_MAX_ROOT_HUB 2
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900381#define R8A66597_MAX_SAMPLING 5
382#define R8A66597_RH_POLL_TIME 10
383
384#define BULK_IN_PIPENUM 3
385#define BULK_IN_BUFNUM 8
386
387#define BULK_OUT_PIPENUM 4
388#define BULK_OUT_BUFNUM 40
389
Marek Vasut8b548302019-08-11 13:44:10 +0200390#define make_devsel(addr) ((addr) << 12)
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900391
392struct r8a66597 {
393 unsigned long reg;
394 unsigned short pipe_config; /* bit field */
395 unsigned short port_status;
396 unsigned short port_change;
397 u16 speed; /* HSMODE or FSMODE or LSMODE */
398 unsigned char rh_devnum;
Marek Vasut769a9cd2019-08-22 17:53:04 +0200399 struct udevice *vbus_supply;
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900400};
401
402static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
403{
Marek Vasut4c9a1352019-08-11 13:20:12 +0200404 return readw(r8a66597->reg + offset);
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900405}
406
407static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
408 unsigned long offset, void *buf,
409 int len)
410{
411 int i;
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900412 unsigned long fifoaddr = r8a66597->reg + offset;
413 unsigned long count;
414 unsigned long *p = buf;
415
416 count = len / 4;
417 for (i = 0; i < count; i++)
Marek Vasut4c9a1352019-08-11 13:20:12 +0200418 p[i] = readl(r8a66597->reg + offset);
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900419
420 if (len & 0x00000003) {
Marek Vasut4c9a1352019-08-11 13:20:12 +0200421 unsigned long tmp = readl(fifoaddr);
Marek Vasut8b548302019-08-11 13:44:10 +0200422
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900423 memcpy((unsigned char *)buf + count * 4, &tmp, len & 0x03);
424 }
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900425}
426
427static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
428 unsigned long offset)
429{
Marek Vasut4c9a1352019-08-11 13:20:12 +0200430 writew(val, r8a66597->reg + offset);
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900431}
432
433static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
434 unsigned long offset, void *buf,
435 int len)
436{
437 int i;
438 unsigned long fifoaddr = r8a66597->reg + offset;
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900439 unsigned long count;
440 unsigned char *pb;
441 unsigned long *p = buf;
442
443 count = len / 4;
444 for (i = 0; i < count; i++)
Marek Vasut4c9a1352019-08-11 13:20:12 +0200445 writel(p[i], fifoaddr);
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900446
447 if (len & 0x00000003) {
448 pb = (unsigned char *)buf + count * 4;
449 for (i = 0; i < (len & 0x00000003); i++) {
450 if (r8a66597_read(r8a66597, CFIFOSEL) & BIGEND)
Marek Vasut4c9a1352019-08-11 13:20:12 +0200451 writeb(pb[i], fifoaddr + i);
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900452 else
Marek Vasut4c9a1352019-08-11 13:20:12 +0200453 writeb(pb[i], fifoaddr + 3 - i);
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900454 }
455 }
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900456}
457
458static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
459 u16 val, u16 pat, unsigned long offset)
460{
461 u16 tmp;
Marek Vasut8b548302019-08-11 13:44:10 +0200462
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900463 tmp = r8a66597_read(r8a66597, offset);
464 tmp = tmp & (~pat);
465 tmp = tmp | val;
466 r8a66597_write(r8a66597, tmp, offset);
467}
468
469#define r8a66597_bclr(r8a66597, val, offset) \
470 r8a66597_mdfy(r8a66597, 0, val, offset)
471#define r8a66597_bset(r8a66597, val, offset) \
472 r8a66597_mdfy(r8a66597, val, 0, offset)
473
474static inline unsigned long get_syscfg_reg(int port)
475{
476 return port == 0 ? SYSCFG0 : SYSCFG1;
477}
478
479static inline unsigned long get_syssts_reg(int port)
480{
481 return port == 0 ? SYSSTS0 : SYSSTS1;
482}
483
484static inline unsigned long get_dvstctr_reg(int port)
485{
486 return port == 0 ? DVSTCTR0 : DVSTCTR1;
487}
488
489static inline unsigned long get_dmacfg_reg(int port)
490{
491 return port == 0 ? DMA0CFG : DMA1CFG;
492}
493
494static inline unsigned long get_intenb_reg(int port)
495{
496 return port == 0 ? INTENB1 : INTENB2;
497}
498
499static inline unsigned long get_intsts_reg(int port)
500{
501 return port == 0 ? INTSTS1 : INTSTS2;
502}
503
504static inline u16 get_rh_usb_speed(struct r8a66597 *r8a66597, int port)
505{
506 unsigned long dvstctr_reg = get_dvstctr_reg(port);
507
508 return r8a66597_read(r8a66597, dvstctr_reg) & RHST;
509}
510
511static inline void r8a66597_port_power(struct r8a66597 *r8a66597, int port,
512 int power)
513{
514 unsigned long dvstctr_reg = get_dvstctr_reg(port);
515
516 if (power)
517 r8a66597_bset(r8a66597, VBOUT, dvstctr_reg);
518 else
519 r8a66597_bclr(r8a66597, VBOUT, dvstctr_reg);
520}
521
522#define get_pipectr_addr(pipenum) (PIPE1CTR + (pipenum - 1) * 2)
523#define get_pipetre_addr(pipenum) (PIPE1TRE + (pipenum - 1) * 4)
524#define get_pipetrn_addr(pipenum) (PIPE1TRN + (pipenum - 1) * 4)
525#define get_devadd_addr(address) (DEVADD0 + address * 2)
526
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900527/* USB HUB CONSTANTS (not OHCI-specific; see hub.h, based on usb_ohci.h) */
528
529/* destination of request */
530#define RH_INTERFACE 0x01
531#define RH_ENDPOINT 0x02
532#define RH_OTHER 0x03
533
534#define RH_CLASS 0x20
535#define RH_VENDOR 0x40
536
537/* Requests: bRequest << 8 | bmRequestType */
538#define RH_GET_STATUS 0x0080
539#define RH_CLEAR_FEATURE 0x0100
540#define RH_SET_FEATURE 0x0300
541#define RH_SET_ADDRESS 0x0500
542#define RH_GET_DESCRIPTOR 0x0680
543#define RH_SET_DESCRIPTOR 0x0700
544#define RH_GET_CONFIGURATION 0x0880
545#define RH_SET_CONFIGURATION 0x0900
546#define RH_GET_STATE 0x0280
547#define RH_GET_INTERFACE 0x0A80
548#define RH_SET_INTERFACE 0x0B00
549#define RH_SYNC_FRAME 0x0C80
550/* Our Vendor Specific Request */
551#define RH_SET_EP 0x2000
552
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900553/* Hub port features */
554#define RH_PORT_CONNECTION 0x00
555#define RH_PORT_ENABLE 0x01
556#define RH_PORT_SUSPEND 0x02
557#define RH_PORT_OVER_CURRENT 0x03
558#define RH_PORT_RESET 0x04
559#define RH_PORT_POWER 0x08
560#define RH_PORT_LOW_SPEED 0x09
561
562#define RH_C_PORT_CONNECTION 0x10
563#define RH_C_PORT_ENABLE 0x11
564#define RH_C_PORT_SUSPEND 0x12
565#define RH_C_PORT_OVER_CURRENT 0x13
566#define RH_C_PORT_RESET 0x14
567
568/* Hub features */
569#define RH_C_HUB_LOCAL_POWER 0x00
570#define RH_C_HUB_OVER_CURRENT 0x01
571
572#define RH_DEVICE_REMOTE_WAKEUP 0x00
573#define RH_ENDPOINT_STALL 0x01
574
575#define RH_ACK 0x01
576#define RH_REQ_ERR -1
577#define RH_NACK 0x00
578
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900579/* OHCI ROOT HUB REGISTER MASKS */
580
581/* roothub.portstatus [i] bits */
582#define RH_PS_CCS 0x00000001 /* current connect status */
583#define RH_PS_PES 0x00000002 /* port enable status*/
584#define RH_PS_PSS 0x00000004 /* port suspend status */
585#define RH_PS_POCI 0x00000008 /* port over current indicator */
586#define RH_PS_PRS 0x00000010 /* port reset status */
587#define RH_PS_PPS 0x00000100 /* port power status */
588#define RH_PS_LSDA 0x00000200 /* low speed device attached */
589#define RH_PS_CSC 0x00010000 /* connect status change */
590#define RH_PS_PESC 0x00020000 /* port enable status change */
591#define RH_PS_PSSC 0x00040000 /* port suspend status change */
592#define RH_PS_OCIC 0x00080000 /* over current indicator change */
593#define RH_PS_PRSC 0x00100000 /* port reset status change */
594
595/* roothub.status bits */
596#define RH_HS_LPS 0x00000001 /* local power status */
597#define RH_HS_OCI 0x00000002 /* over current indicator */
598#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
599#define RH_HS_LPSC 0x00010000 /* local power status change */
600#define RH_HS_OCIC 0x00020000 /* over current indicator change */
601#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
602
603/* roothub.b masks */
604#define RH_B_DR 0x0000ffff /* device removable flags */
605#define RH_B_PPCM 0xffff0000 /* port power control mask */
606
607/* roothub.a masks */
608#define RH_A_NDP (0xff << 0) /* number of downstream ports */
Marek Vasut8b548302019-08-11 13:44:10 +0200609#define RH_A_PSM BIT(8) /* power switching mode */
610#define RH_A_NPS BIT(9) /* no power switching */
611#define RH_A_DT BIT(10) /* device type (mbz) */
612#define RH_A_OCPM BIT(11) /* over current protection mode */
613#define RH_A_NOCP BIT(12) /* no over current protection */
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900614#define RH_A_POTPGT (0xff << 24) /* power on to power good time */
615
Yoshihiro Shimodafd0f2f32008-07-09 21:07:38 +0900616#endif /* __R8A66597_H__ */