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Matt Waddelb80e41a2010-10-07 15:48:45 -06001/*
Ryan Harkincd4f46e2013-04-09 02:20:31 +00002 * (C) Copyright 2011 ARM Limited
Matt Waddelb80e41a2010-10-07 15:48:45 -06003 * (C) Copyright 2010 Linaro
4 * Matt Waddel, <matt.waddel@linaro.org>
5 *
6 * Configuration for Versatile Express. Parts were derived from other ARM
7 * configurations.
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
Ryan Harkincd4f46e2013-04-09 02:20:31 +000028#ifndef __VEXPRESS_COMMON_H
29#define __VEXPRESS_COMMON_H
30
31/*
32 * Definitions copied from linux kernel:
33 * arch/arm/mach-vexpress/include/mach/motherboard.h
34 */
35#ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
36/* CS register bases for the original memory map. */
37#define V2M_PA_CS0 0x40000000
38#define V2M_PA_CS1 0x44000000
39#define V2M_PA_CS2 0x48000000
40#define V2M_PA_CS3 0x4c000000
41#define V2M_PA_CS7 0x10000000
42
43#define V2M_PERIPH_OFFSET(x) (x << 12)
44#define V2M_SYSREGS (V2M_PA_CS7 + V2M_PERIPH_OFFSET(0))
45#define V2M_SYSCTL (V2M_PA_CS7 + V2M_PERIPH_OFFSET(1))
46#define V2M_SERIAL_BUS_PCI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(2))
47
48#define V2M_BASE 0x60000000
49#define CONFIG_SYS_TEXT_BASE 0x60800000
50#elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP)
51/* CS register bases for the extended memory map. */
52#define V2M_PA_CS0 0x08000000
53#define V2M_PA_CS1 0x0c000000
54#define V2M_PA_CS2 0x14000000
55#define V2M_PA_CS3 0x18000000
56#define V2M_PA_CS7 0x1c000000
57
58#define V2M_PERIPH_OFFSET(x) (x << 16)
59#define V2M_SYSREGS (V2M_PA_CS7 + V2M_PERIPH_OFFSET(1))
60#define V2M_SYSCTL (V2M_PA_CS7 + V2M_PERIPH_OFFSET(2))
61#define V2M_SERIAL_BUS_PCI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(3))
62
63#define V2M_BASE 0x80000000
64#define CONFIG_SYS_TEXT_BASE 0x80800000
65#endif
66
67/*
68 * Physical addresses, offset from V2M_PA_CS0-3
69 */
70#define V2M_NOR0 (V2M_PA_CS0)
71#define V2M_NOR1 (V2M_PA_CS1)
72#define V2M_SRAM (V2M_PA_CS2)
73#define V2M_VIDEO_SRAM (V2M_PA_CS3 + 0x00000000)
74#define V2M_LAN9118 (V2M_PA_CS3 + 0x02000000)
75#define V2M_ISP1761 (V2M_PA_CS3 + 0x03000000)
76
77/* Common peripherals relative to CS7. */
78#define V2M_AACI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(4))
79#define V2M_MMCI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(5))
80#define V2M_KMI0 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(6))
81#define V2M_KMI1 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(7))
82
83#define V2M_UART0 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(9))
84#define V2M_UART1 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(10))
85#define V2M_UART2 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(11))
86#define V2M_UART3 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(12))
87
88#define V2M_WDT (V2M_PA_CS7 + V2M_PERIPH_OFFSET(15))
89
90#define V2M_TIMER01 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(17))
91#define V2M_TIMER23 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(18))
92
93#define V2M_SERIAL_BUS_DVI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(22))
94#define V2M_RTC (V2M_PA_CS7 + V2M_PERIPH_OFFSET(23))
95
96#define V2M_CF (V2M_PA_CS7 + V2M_PERIPH_OFFSET(26))
97
98#define V2M_CLCD (V2M_PA_CS7 + V2M_PERIPH_OFFSET(31))
99#define V2M_SIZE_CS7 V2M_PERIPH_OFFSET(32)
100
101/* System register offsets. */
102#define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0)
103#define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4)
104#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8)
105
106/*
107 * Configuration
108 */
109#define SYS_CFG_START (1 << 31)
110#define SYS_CFG_WRITE (1 << 30)
111#define SYS_CFG_OSC (1 << 20)
112#define SYS_CFG_VOLT (2 << 20)
113#define SYS_CFG_AMP (3 << 20)
114#define SYS_CFG_TEMP (4 << 20)
115#define SYS_CFG_RESET (5 << 20)
116#define SYS_CFG_SCC (6 << 20)
117#define SYS_CFG_MUXFPGA (7 << 20)
118#define SYS_CFG_SHUTDOWN (8 << 20)
119#define SYS_CFG_REBOOT (9 << 20)
120#define SYS_CFG_DVIMODE (11 << 20)
121#define SYS_CFG_POWER (12 << 20)
122#define SYS_CFG_SITE_MB (0 << 16)
123#define SYS_CFG_SITE_DB1 (1 << 16)
124#define SYS_CFG_SITE_DB2 (2 << 16)
125#define SYS_CFG_STACK(n) ((n) << 12)
126
127#define SYS_CFG_ERR (1 << 1)
128#define SYS_CFG_COMPLETE (1 << 0)
Matt Waddelb80e41a2010-10-07 15:48:45 -0600129
130/* Board info register */
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000131#define SYS_ID V2M_SYSREGS
Matt Waddelb80e41a2010-10-07 15:48:45 -0600132#define CONFIG_REVISION_TAG 1
133
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000134#define CONFIG_SYS_MEMTEST_START V2M_BASE
Matt Waddelb80e41a2010-10-07 15:48:45 -0600135#define CONFIG_SYS_MEMTEST_END 0x20000000
136#define CONFIG_SYS_HZ 1000
137
138#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
139#define CONFIG_SETUP_MEMORY_TAGS 1
Aneesh Ve47f2db2011-06-16 23:30:48 +0000140#define CONFIG_SYS_L2CACHE_OFF 1
Matt Waddelb80e41a2010-10-07 15:48:45 -0600141#define CONFIG_INITRD_TAG 1
142
Grant Likely2fa8ca92011-03-28 09:59:07 +0000143#define CONFIG_OF_LIBFDT 1
144
Matt Waddelb80e41a2010-10-07 15:48:45 -0600145/* Size of malloc() pool */
146#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
Matt Waddelb80e41a2010-10-07 15:48:45 -0600147
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000148#define SCTL_BASE V2M_SYSCTL
Matt Waddelb80e41a2010-10-07 15:48:45 -0600149#define VEXPRESS_FLASHPROG_FLVPPEN (1 << 0)
150
151/* SMSC9115 Ethernet from SMSC9118 family */
Matt Waddelb80e41a2010-10-07 15:48:45 -0600152#define CONFIG_SMC911X 1
153#define CONFIG_SMC911X_32_BIT 1
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000154#define CONFIG_SMC911X_BASE V2M_LAN9118
Matt Waddelb80e41a2010-10-07 15:48:45 -0600155
156/* PL011 Serial Configuration */
157#define CONFIG_PL011_SERIAL
158#define CONFIG_PL011_CLOCK 24000000
159#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
160 (void *)CONFIG_SYS_SERIAL1}
161#define CONFIG_CONS_INDEX 0
162
163#define CONFIG_BAUDRATE 38400
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000164#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
165#define CONFIG_SYS_SERIAL0 V2M_UART0
166#define CONFIG_SYS_SERIAL1 V2M_UART1
Matt Waddelb80e41a2010-10-07 15:48:45 -0600167
168/* Command line configuration */
169#define CONFIG_CMD_BDI
170#define CONFIG_CMD_DHCP
Jason Hobbse21669f2011-08-23 11:07:00 +0000171#define CONFIG_CMD_PXE
172#define CONFIG_MENU
Matt Waddelb80e41a2010-10-07 15:48:45 -0600173#define CONFIG_CMD_ELF
174#define CONFIG_CMD_ENV
175#define CONFIG_CMD_FLASH
176#define CONFIG_CMD_IMI
177#define CONFIG_CMD_MEMORY
178#define CONFIG_CMD_NET
179#define CONFIG_CMD_PING
180#define CONFIG_CMD_SAVEENV
Matt Waddelb80e41a2010-10-07 15:48:45 -0600181#define CONFIG_CMD_RUN
Andre Przywarad21c3af2013-04-09 02:20:33 +0000182#define CONFIG_CMD_BOOTZ
183#define CONFIG_SUPPORT_RAW_INITRD
Matt Waddelb80e41a2010-10-07 15:48:45 -0600184
185#define CONFIG_CMD_FAT
186#define CONFIG_DOS_PARTITION 1
187#define CONFIG_MMC 1
188#define CONFIG_CMD_MMC
189#define CONFIG_GENERIC_MMC
Matt Waddelf0c64522011-04-16 11:54:08 +0000190#define CONFIG_ARM_PL180_MMCI
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000191#define CONFIG_ARM_PL180_MMCI_BASE V2M_MMCI
Matt Waddelf0c64522011-04-16 11:54:08 +0000192#define CONFIG_SYS_MMC_MAX_BLK_COUNT 127
193#define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 6250000
Matt Waddelb80e41a2010-10-07 15:48:45 -0600194
195/* BOOTP options */
196#define CONFIG_BOOTP_BOOTFILESIZE
197#define CONFIG_BOOTP_BOOTPATH
198#define CONFIG_BOOTP_GATEWAY
199#define CONFIG_BOOTP_HOSTNAME
Jason Hobbse72f0b12011-08-23 11:07:01 +0000200#define CONFIG_BOOTP_PXE
201#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100
Matt Waddelb80e41a2010-10-07 15:48:45 -0600202
203/* Miscellaneous configurable options */
204#undef CONFIG_SYS_CLKS_IN_HZ
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000205#define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x8000)
206#define LINUX_BOOT_PARAM_ADDR (V2M_BASE + 0x2000)
Matt Waddelb80e41a2010-10-07 15:48:45 -0600207#define CONFIG_BOOTDELAY 2
208
Matt Waddelb80e41a2010-10-07 15:48:45 -0600209/* Physical Memory Map */
210#define CONFIG_NR_DRAM_BANKS 2
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000211#define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */
212#define PHYS_SDRAM_2 (((unsigned int)V2M_BASE) + \
213 ((unsigned int)0x20000000))
Matt Waddelb80e41a2010-10-07 15:48:45 -0600214#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
215#define PHYS_SDRAM_2_SIZE 0x20000000 /* 512 MB */
216
217/* additions for new relocation code */
218#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
Wolfgang Denk553f0982010-10-26 13:32:32 +0200219#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
Matt Waddelb80e41a2010-10-07 15:48:45 -0600220#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200221 CONFIG_SYS_INIT_RAM_SIZE - \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200222 GENERATED_GBL_DATA_SIZE)
Matt Waddelb80e41a2010-10-07 15:48:45 -0600223#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET
224
225/* Basic environment settings */
226#define CONFIG_BOOTCOMMAND "run bootflash;"
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000227#ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
228#define CONFIG_PLATFORM_ENV_SETTINGS \
Matt Waddelb80e41a2010-10-07 15:48:45 -0600229 "loadaddr=0x80008000\0" \
Jason Hobbs75e7f3f2011-08-23 11:06:59 +0000230 "ramdisk_addr_r=0x61000000\0" \
231 "kernel_addr=0x44100000\0" \
232 "ramdisk_addr=0x44800000\0" \
233 "maxramdisk=0x1800000\0" \
Jason Hobbse21669f2011-08-23 11:07:00 +0000234 "pxefile_addr_r=0x88000000\0" \
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000235 "kernel_addr_r=0x80008000\0"
236#elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP)
237#define CONFIG_PLATFORM_ENV_SETTINGS \
238 "loadaddr=0xa0008000\0" \
239 "ramdisk_addr_r=0x81000000\0" \
240 "kernel_addr=0x0c100000\0" \
241 "ramdisk_addr=0x0c800000\0" \
242 "maxramdisk=0x1800000\0" \
243 "pxefile_addr_r=0xa8000000\0" \
244 "kernel_addr_r=0xa0008000\0"
245#endif
246#define CONFIG_EXTRA_ENV_SETTINGS \
247 CONFIG_PLATFORM_ENV_SETTINGS \
Matt Waddelb80e41a2010-10-07 15:48:45 -0600248 "console=ttyAMA0,38400n8\0" \
249 "dram=1024M\0" \
250 "root=/dev/sda1 rw\0" \
251 "mtd=armflash:1M@0x800000(uboot),7M@0x1000000(kernel)," \
252 "24M@0x2000000(initrd)\0" \
253 "flashargs=setenv bootargs root=${root} console=${console} " \
254 "mem=${dram} mtdparts=${mtd} mmci.fmax=190000 " \
255 "devtmpfs.mount=0 vmalloc=256M\0" \
256 "bootflash=run flashargs; " \
Jason Hobbs75e7f3f2011-08-23 11:06:59 +0000257 "cp ${ramdisk_addr} ${ramdisk_addr_r} ${maxramdisk}; " \
258 "bootm ${kernel_addr} ${ramdisk_addr_r}\0"
Matt Waddelb80e41a2010-10-07 15:48:45 -0600259
260/* FLASH and environment organization */
261#define PHYS_FLASH_SIZE 0x04000000 /* 64MB */
262#define CONFIG_SYS_FLASH_CFI 1
263#define CONFIG_FLASH_CFI_DRIVER 1
264#define CONFIG_SYS_FLASH_SIZE 0x04000000
265#define CONFIG_SYS_MAX_FLASH_BANKS 2
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000266#define CONFIG_SYS_FLASH_BASE0 V2M_NOR0
267#define CONFIG_SYS_FLASH_BASE1 V2M_NOR1
Matt Waddelb80e41a2010-10-07 15:48:45 -0600268#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE0
269
270/* Timeout values in ticks */
271#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */
272#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */
273
274/* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */
275#define CONFIG_SYS_MAX_FLASH_SECT 259 /* Max sectors */
276#define FLASH_MAX_SECTOR_SIZE 0x00040000 /* 256 KB sectors */
277
278/* Room required on the stack for the environment data */
279#define CONFIG_ENV_SIZE FLASH_MAX_SECTOR_SIZE
280
402jagan@gmail.comde1f9ac2012-07-29 04:26:08 +0000281#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
282
Matt Waddelb80e41a2010-10-07 15:48:45 -0600283/*
284 * Amount of flash used for environment:
285 * We don't know which end has the small erase blocks so we use the penultimate
286 * sector location for the environment
287 */
288#define CONFIG_ENV_SECT_SIZE FLASH_MAX_SECTOR_SIZE
289#define CONFIG_ENV_OVERWRITE 1
290
291/* Store environment at top of flash */
292#define CONFIG_ENV_IS_IN_FLASH 1
293#define CONFIG_ENV_OFFSET (PHYS_FLASH_SIZE - \
294 (2 * CONFIG_ENV_SECT_SIZE))
295#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE1 + \
296 CONFIG_ENV_OFFSET)
297#define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */
298#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
299#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE0, \
300 CONFIG_SYS_FLASH_BASE1 }
301
302/* Monitor Command Prompt */
303#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
304#define CONFIG_SYS_PROMPT "VExpress# "
305#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
306 sizeof(CONFIG_SYS_PROMPT) + 16)
Andre Przywarad21c3af2013-04-09 02:20:33 +0000307#define CONFIG_SYS_HUSH_PARSER
308
Matt Waddelb80e41a2010-10-07 15:48:45 -0600309#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
310#define CONFIG_CMD_SOURCE
311#define CONFIG_SYS_LONGHELP
312#define CONFIG_CMDLINE_EDITING 1
313#define CONFIG_SYS_MAXARGS 16 /* max command args */
314
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000315#endif /* VEXPRESS_COMMON_H */