blob: b91c6130e7847f4c9b50b893b6c37a6167cc126e [file] [log] [blame]
Eran Libertyf046ccd2005-07-28 10:08:46 -05001/*
Dave Liuf6eda7f2006-10-25 14:41:21 -05002 * (C) Copyright 2006 Freescale Semiconductor, Inc.
3 *
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +01004 * (C) Copyright 2006
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
Wolfgang Denkcf48eb92006-04-16 10:51:58 +02006 *
Dave Liu5f820432006-11-03 19:33:44 -06007 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
Eran Libertyf046ccd2005-07-28 10:08:46 -05008 * (C) Copyright 2003 Motorola Inc.
9 * Xianghua Xiao (X.Xiao@motorola.com)
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 *
29 * Change log:
30 *
31 * 20050101: Eran Liberty (liberty@freescale.com)
32 * Initial file creating (porting from 85XX & 8260)
Dave Liuf6eda7f2006-10-25 14:41:21 -050033 * 20060601: Dave Liu (daveliu@freescale.com)
34 * DDR ECC support
35 * unify variable names for 83xx
36 * code cleanup
Eran Libertyf046ccd2005-07-28 10:08:46 -050037 */
38
39#include <common.h>
40#include <asm/processor.h>
41#include <i2c.h>
42#include <spd.h>
43#include <asm/mmu.h>
44#include <spd_sdram.h>
45
46#ifdef CONFIG_SPD_EEPROM
47
Dave Liuf6eda7f2006-10-25 14:41:21 -050048#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
Eran Libertyf046ccd2005-07-28 10:08:46 -050049extern void dma_init(void);
50extern uint dma_check(void);
51extern int dma_xfer(void *dest, uint count, void *src);
52#endif
53
Eran Libertyf046ccd2005-07-28 10:08:46 -050054#ifndef CFG_READ_SPD
55#define CFG_READ_SPD i2c_read
56#endif
57
Eran Libertyf046ccd2005-07-28 10:08:46 -050058/*
59 * Convert picoseconds into clock cycles (rounding up if needed).
60 */
Dave Liuf6eda7f2006-10-25 14:41:21 -050061extern ulong get_ddr_clk(ulong dummy);
Eran Libertyf046ccd2005-07-28 10:08:46 -050062
63int
64picos_to_clk(int picos)
65{
Dave Liuf6eda7f2006-10-25 14:41:21 -050066 unsigned int ddr_bus_clk;
Eran Libertyf046ccd2005-07-28 10:08:46 -050067 int clks;
68
Dave Liuf6eda7f2006-10-25 14:41:21 -050069 ddr_bus_clk = get_ddr_clk(0) >> 1;
70 clks = picos / ((1000000000 / ddr_bus_clk) * 1000);
71 if (picos % ((1000000000 / ddr_bus_clk) * 1000) !=0) {
72 clks++;
Eran Libertyf046ccd2005-07-28 10:08:46 -050073 }
74
75 return clks;
76}
77
Marian Balakowicz4c8d1ec2006-03-14 16:23:35 +010078unsigned int banksize(unsigned char row_dens)
Eran Libertyf046ccd2005-07-28 10:08:46 -050079{
80 return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
81}
82
Marian Balakowicz4c8d1ec2006-03-14 16:23:35 +010083int read_spd(uint addr)
84{
85 return ((int) addr);
86}
87
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +010088#undef SPD_DEBUG
89#ifdef SPD_DEBUG
90static void spd_debug(spd_eeprom_t *spd)
91{
92 printf ("\nDIMM type: %-18.18s\n", spd->mpart);
93 printf ("SPD size: %d\n", spd->info_size);
94 printf ("EEPROM size: %d\n", 1 << spd->chip_size);
95 printf ("Memory type: %d\n", spd->mem_type);
96 printf ("Row addr: %d\n", spd->nrow_addr);
97 printf ("Column addr: %d\n", spd->ncol_addr);
98 printf ("# of rows: %d\n", spd->nrows);
99 printf ("Row density: %d\n", spd->row_dens);
100 printf ("# of banks: %d\n", spd->nbanks);
101 printf ("Data width: %d\n",
102 256 * spd->dataw_msb + spd->dataw_lsb);
103 printf ("Chip width: %d\n", spd->primw);
104 printf ("Refresh rate: %02X\n", spd->refresh);
105 printf ("CAS latencies: %02X\n", spd->cas_lat);
106 printf ("Write latencies: %02X\n", spd->write_lat);
107 printf ("tRP: %d\n", spd->trp);
108 printf ("tRCD: %d\n", spd->trcd);
109 printf ("\n");
110}
111#endif /* SPD_DEBUG */
112
113long int spd_sdram()
Eran Libertyf046ccd2005-07-28 10:08:46 -0500114{
115 volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
Dave Liuf6eda7f2006-10-25 14:41:21 -0500116 volatile ddr83xx_t *ddr = &immap->ddr;
117 volatile law83xx_t *ecm = &immap->sysconf.ddrlaw[0];
Eran Libertyf046ccd2005-07-28 10:08:46 -0500118 spd_eeprom_t spd;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500119 unsigned int memsize;
120 unsigned int law_size;
Dave Liuf6eda7f2006-10-25 14:41:21 -0500121 unsigned char caslat, caslat_ctrl;
122 unsigned char burstlen;
123 unsigned int max_bus_clk;
124 unsigned int max_data_rate, effective_data_rate;
125 unsigned int ddrc_clk;
126 unsigned int refresh_clk;
127 unsigned sdram_cfg;
128 unsigned int ddrc_ecc_enable;
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500129
Dave Liuf6eda7f2006-10-25 14:41:21 -0500130 /* Read SPD parameters with I2C */
Eran Libertyf046ccd2005-07-28 10:08:46 -0500131 CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +0100132#ifdef SPD_DEBUG
133 spd_debug(&spd);
134#endif
Dave Liuf6eda7f2006-10-25 14:41:21 -0500135 /* Check the memory type */
136 if (spd.mem_type != SPD_MEMTYPE_DDR) {
137 printf("DDR: Module mem type is %02X\n", spd.mem_type);
138 return 0;
139 }
140
141 /* Check the number of physical bank */
Eran Libertyf046ccd2005-07-28 10:08:46 -0500142 if (spd.nrows > 2) {
Dave Liuf6eda7f2006-10-25 14:41:21 -0500143 printf("DDR: The number of physical bank is %02X\n", spd.nrows);
Eran Libertyf046ccd2005-07-28 10:08:46 -0500144 return 0;
145 }
146
Dave Liuf6eda7f2006-10-25 14:41:21 -0500147 /* Check if the number of row of the module is in the range of DDRC */
148 if (spd.nrow_addr < 12 || spd.nrow_addr > 14) {
149 printf("DDR: Row number is out of range of DDRC, row=%02X\n",
150 spd.nrow_addr);
Eran Libertyf046ccd2005-07-28 10:08:46 -0500151 return 0;
152 }
153
Dave Liuf6eda7f2006-10-25 14:41:21 -0500154 /* Check if the number of col of the module is in the range of DDRC */
155 if (spd.ncol_addr < 8 || spd.ncol_addr > 11) {
156 printf("DDR: Col number is out of range of DDRC, col=%02X\n",
157 spd.ncol_addr);
158 return 0;
159 }
160 /* Setup DDR chip select register */
Dave Liu5f820432006-11-03 19:33:44 -0600161#ifdef CFG_83XX_DDR_USES_CS0
162 ddr->csbnds[0].csbnds = (banksize(spd.row_dens) >> 24) - 1;
163 ddr->cs_config[0] = ( 1 << 31
164 | (spd.nrow_addr - 12) << 8
165 | (spd.ncol_addr - 8) );
166 debug("\n");
167 debug("cs0_bnds = 0x%08x\n",ddr->csbnds[0].csbnds);
168 debug("cs0_config = 0x%08x\n",ddr->cs_config[0]);
169
170 if (spd.nrows == 2) {
171 ddr->csbnds[1].csbnds = ( (banksize(spd.row_dens) >> 8)
172 | ((banksize(spd.row_dens) >> 23) - 1) );
173 ddr->cs_config[1] = ( 1<<31
174 | (spd.nrow_addr-12) << 8
175 | (spd.ncol_addr-8) );
176 debug("cs1_bnds = 0x%08x\n",ddr->csbnds[1].csbnds);
177 debug("cs1_config = 0x%08x\n",ddr->cs_config[1]);
178 }
179
180#else
Eran Libertyf046ccd2005-07-28 10:08:46 -0500181 ddr->csbnds[2].csbnds = (banksize(spd.row_dens) >> 24) - 1;
182 ddr->cs_config[2] = ( 1 << 31
183 | (spd.nrow_addr - 12) << 8
184 | (spd.ncol_addr - 8) );
185 debug("\n");
186 debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds);
187 debug("cs2_config = 0x%08x\n",ddr->cs_config[2]);
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500188
Eran Libertyf046ccd2005-07-28 10:08:46 -0500189 if (spd.nrows == 2) {
190 ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8)
191 | ((banksize(spd.row_dens) >> 23) - 1) );
192 ddr->cs_config[3] = ( 1<<31
193 | (spd.nrow_addr-12) << 8
194 | (spd.ncol_addr-8) );
195 debug("cs3_bnds = 0x%08x\n",ddr->csbnds[3].csbnds);
196 debug("cs3_config = 0x%08x\n",ddr->cs_config[3]);
197 }
Timur Tabi2ad6b512006-10-31 18:44:42 -0600198#endif
Eran Libertyf046ccd2005-07-28 10:08:46 -0500199
200 if (spd.mem_type != 0x07) {
201 puts("No DDR module found!\n");
202 return 0;
203 }
204
205 /*
206 * Figure out memory size in Megabytes.
207 */
208 memsize = spd.nrows * banksize(spd.row_dens) / 0x100000;
209
210 /*
211 * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23.
212 */
213 law_size = 19 + __ilog2(memsize);
214
215 /*
216 * Set up LAWBAR for all of DDR.
217 */
218 ecm->bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
219 ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
220 debug("DDR:bar=0x%08x\n", ecm->bar);
221 debug("DDR:ar=0x%08x\n", ecm->ar);
222
223 /*
Dave Liuf6eda7f2006-10-25 14:41:21 -0500224 * Find the largest CAS by locating the highest 1 bit
225 * in the spd.cas_lat field. Translate it to a DDR
226 * controller field value:
227 *
228 * CAS Lat DDR I Ctrl
229 * Clocks SPD Bit Value
230 * -------+--------+---------
231 * 1.0 0 001
232 * 1.5 1 010
233 * 2.0 2 011
234 * 2.5 3 100
235 * 3.0 4 101
236 * 3.5 5 110
237 * 4.0 6 111
Eran Libertyf046ccd2005-07-28 10:08:46 -0500238 */
Dave Liuf6eda7f2006-10-25 14:41:21 -0500239 caslat = __ilog2(spd.cas_lat);
240
Dave Liu5f820432006-11-03 19:33:44 -0600241 if (caslat > 6 ) {
242 printf("DDR: Invalid SPD CAS Latency, caslat=%02X\n",
243 spd.cas_lat);
Eran Libertyf046ccd2005-07-28 10:08:46 -0500244 return 0;
245 }
Dave Liuf6eda7f2006-10-25 14:41:21 -0500246 max_bus_clk = 1000 *10 / (((spd.clk_cycle & 0xF0) >> 4) * 10
247 + (spd.clk_cycle & 0x0f));
248 max_data_rate = max_bus_clk * 2;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500249
Dave Liuf6eda7f2006-10-25 14:41:21 -0500250 debug("DDR:Module maximum data rate is: %dMhz\n", max_data_rate);
Eran Libertyf046ccd2005-07-28 10:08:46 -0500251
Dave Liuf6eda7f2006-10-25 14:41:21 -0500252 ddrc_clk = get_ddr_clk(0) / 1000000;
253
254 if (max_data_rate >= 390) { /* it is DDR 400 */
Dave Liu5f820432006-11-03 19:33:44 -0600255 if (ddrc_clk <= 410 && ddrc_clk > 350) {
256 /* DDR controller clk at 350~410 */
257 effective_data_rate = 400; /* 5ns */
258 caslat = caslat;
259 } else if (ddrc_clk <= 350 && ddrc_clk > 280) {
260 /* DDR controller clk at 280~350 */
261 effective_data_rate = 333; /* 6ns */
262 if (spd.clk_cycle2 == 0x60) {
263 caslat = caslat - 1;
264 } else {
265 caslat = caslat;
266 }
267 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
268 /* DDR controller clk at 230~280 */
269 effective_data_rate = 266; /* 7.5ns */
270 if (spd.clk_cycle3 == 0x75) {
271 caslat = caslat - 2;
272 } else if (spd.clk_cycle2 == 0x60) {
273 caslat = caslat - 1;
274 } else {
275 caslat = caslat;
276 }
277 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
278 /* DDR controller clk at 90~230 */
279 effective_data_rate = 200; /* 10ns */
280 if (spd.clk_cycle3 == 0x75) {
281 caslat = caslat - 2;
282 } else if (spd.clk_cycle2 == 0x60) {
283 caslat = caslat - 1;
284 } else {
285 caslat = caslat;
286 }
287 }
Dave Liuf6eda7f2006-10-25 14:41:21 -0500288 } else if (max_data_rate >= 323) { /* it is DDR 333 */
289 if (ddrc_clk <= 350 && ddrc_clk > 280) {
Dave Liu5f820432006-11-03 19:33:44 -0600290 /* DDR controller clk at 280~350 */
Dave Liuf6eda7f2006-10-25 14:41:21 -0500291 effective_data_rate = 333; /* 6ns */
292 caslat = caslat;
293 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
Dave Liu5f820432006-11-03 19:33:44 -0600294 /* DDR controller clk at 230~280 */
295 effective_data_rate = 266; /* 7.5ns */
Dave Liuf6eda7f2006-10-25 14:41:21 -0500296 if (spd.clk_cycle2 == 0x75) {
Dave Liuf6eda7f2006-10-25 14:41:21 -0500297 caslat = caslat - 1;
Dave Liu5f820432006-11-03 19:33:44 -0600298 } else {
299 caslat = caslat;
Dave Liuf6eda7f2006-10-25 14:41:21 -0500300 }
301 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
Dave Liu5f820432006-11-03 19:33:44 -0600302 /* DDR controller clk at 90~230 */
303 effective_data_rate = 200; /* 10ns */
Dave Liuf6eda7f2006-10-25 14:41:21 -0500304 if (spd.clk_cycle3 == 0xa0) {
Dave Liuf6eda7f2006-10-25 14:41:21 -0500305 caslat = caslat - 2;
Dave Liu5f820432006-11-03 19:33:44 -0600306 } else if (spd.clk_cycle2 == 0x75) {
307 caslat = caslat - 1;
308 } else {
309 caslat = caslat;
Dave Liuf6eda7f2006-10-25 14:41:21 -0500310 }
311 }
312 } else if (max_data_rate >= 256) { /* it is DDR 266 */
313 if (ddrc_clk <= 350 && ddrc_clk > 280) {
Dave Liu5f820432006-11-03 19:33:44 -0600314 /* DDR controller clk at 280~350 */
Dave Liuf6eda7f2006-10-25 14:41:21 -0500315 printf("DDR: DDR controller freq is more than "
316 "max data rate of the module\n");
317 return 0;
318 } else if (ddrc_clk <= 280 && ddrc_clk > 230) {
Dave Liu5f820432006-11-03 19:33:44 -0600319 /* DDR controller clk at 230~280 */
Dave Liuf6eda7f2006-10-25 14:41:21 -0500320 effective_data_rate = 266; /* 7.5ns */
321 caslat = caslat;
322 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
Dave Liu5f820432006-11-03 19:33:44 -0600323 /* DDR controller clk at 90~230 */
324 effective_data_rate = 200; /* 10ns */
Dave Liuf6eda7f2006-10-25 14:41:21 -0500325 if (spd.clk_cycle2 == 0xa0) {
Dave Liuf6eda7f2006-10-25 14:41:21 -0500326 caslat = caslat - 1;
327 }
328 }
329 } else if (max_data_rate >= 190) { /* it is DDR 200 */
330 if (ddrc_clk <= 350 && ddrc_clk > 230) {
Dave Liu5f820432006-11-03 19:33:44 -0600331 /* DDR controller clk at 230~350 */
Dave Liuf6eda7f2006-10-25 14:41:21 -0500332 printf("DDR: DDR controller freq is more than "
333 "max data rate of the module\n");
334 return 0;
335 } else if (ddrc_clk <= 230 && ddrc_clk > 90) {
Dave Liu5f820432006-11-03 19:33:44 -0600336 /* DDR controller clk at 90~230 */
Dave Liuf6eda7f2006-10-25 14:41:21 -0500337 effective_data_rate = 200; /* 10ns */
338 caslat = caslat;
339 }
Eran Libertyf046ccd2005-07-28 10:08:46 -0500340 }
341
Dave Liu5f820432006-11-03 19:33:44 -0600342 debug("DDR:Effective data rate is: %dMhz\n", effective_data_rate);
343 debug("DDR:The MSB 1 of CAS Latency is: %d\n", caslat);
Timur Tabibed85ca2006-10-31 18:13:36 -0600344
Dave Liu5f820432006-11-03 19:33:44 -0600345 /*
346 * Errata DDR6 work around: input enable 2 cycles earlier.
347 * including MPC834x Rev1.0/1.1 and MPC8360 Rev1.1/1.2.
348 */
349 if (caslat == 2) {
350 ddr->debug_reg = 0x201c0000; /* CL=2 */
351 } else if (caslat == 3) {
352 ddr->debug_reg = 0x202c0000; /* CL=2.5 */
353 } else if (caslat == 4) {
354 ddr->debug_reg = 0x202c0000; /* CL=3.0 */
Timur Tabibed85ca2006-10-31 18:13:36 -0600355 }
Dave Liu5f820432006-11-03 19:33:44 -0600356 __asm__ __volatile__ ("sync");
Timur Tabibed85ca2006-10-31 18:13:36 -0600357
Dave Liu5f820432006-11-03 19:33:44 -0600358 debug("Errata DDR6 (debug_reg=0x%08x)\n", ddr->debug_reg);
Timur Tabibed85ca2006-10-31 18:13:36 -0600359
Eran Libertyf046ccd2005-07-28 10:08:46 -0500360 /*
361 * note: caslat must also be programmed into ddr->sdram_mode
362 * register.
363 *
364 * note: WRREC(Twr) and WRTORD(Twtr) are not in SPD,
365 * use conservative value here.
366 */
Dave Liuf6eda7f2006-10-25 14:41:21 -0500367 caslat_ctrl = (caslat + 1) & 0x07; /* see as above */
Eran Libertyf046ccd2005-07-28 10:08:46 -0500368
369 ddr->timing_cfg_1 =
370 (((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) |
371 ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) |
372 ((picos_to_clk(spd.trcd * 250) & 0x07) << 20 ) |
Dave Liuf6eda7f2006-10-25 14:41:21 -0500373 ((caslat_ctrl & 0x07) << 16 ) |
374 (((picos_to_clk(spd.trfc * 1000) - 8) & 0x0f) << 12 ) |
Eran Libertyf046ccd2005-07-28 10:08:46 -0500375 ( 0x300 ) |
376 ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | 1);
377
378 ddr->timing_cfg_2 = 0x00000800;
379
380 debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1);
381 debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
Dave Liuf6eda7f2006-10-25 14:41:21 -0500382 /* Setup init value, but not enable */
383 ddr->sdram_cfg = 0x42000000;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500384
Dave Liuf6eda7f2006-10-25 14:41:21 -0500385 /* Check DIMM data bus width */
Dave Liu5f820432006-11-03 19:33:44 -0600386 if (spd.dataw_lsb == 0x20) {
Dave Liuf6eda7f2006-10-25 14:41:21 -0500387 burstlen = 0x03; /* 32 bit data bus, burst len is 8 */
388 printf("\n DDR DIMM: data bus width is 32 bit");
Dave Liu5f820432006-11-03 19:33:44 -0600389 } else {
Dave Liuf6eda7f2006-10-25 14:41:21 -0500390 burstlen = 0x02; /* Others act as 64 bit bus, burst len is 4 */
391 printf("\n DDR DIMM: data bus width is 64 bit");
392 }
393
394 /* Is this an ECC DDR chip? */
395 if (spd.config == 0x02) {
396 printf(" with ECC\n");
Dave Liu5f820432006-11-03 19:33:44 -0600397 } else {
Dave Liuf6eda7f2006-10-25 14:41:21 -0500398 printf(" without ECC\n");
Dave Liu5f820432006-11-03 19:33:44 -0600399 }
Dave Liuf6eda7f2006-10-25 14:41:21 -0500400
401 /* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus,
402 Burst type is sequential
Eran Libertyf046ccd2005-07-28 10:08:46 -0500403 */
Dave Liu5f820432006-11-03 19:33:44 -0600404 switch (caslat) {
405 case 1:
406 ddr->sdram_mode = 0x50 | burstlen; /* CL=1.5 */
407 break;
408 case 2:
409 ddr->sdram_mode = 0x20 | burstlen; /* CL=2.0 */
410 break;
411 case 3:
412 ddr->sdram_mode = 0x60 | burstlen; /* CL=2.5 */
413 break;
414 case 4:
415 ddr->sdram_mode = 0x30 | burstlen; /* CL=3.0 */
416 break;
417 default:
418 printf("DDR:only CL 1.5, 2.0, 2.5, 3.0 is supported\n");
419 return 0;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500420 }
421 debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
422
Dave Liu5f820432006-11-03 19:33:44 -0600423 switch (spd.refresh) {
424 case 0x00:
425 case 0x80:
426 refresh_clk = picos_to_clk(15625000);
427 break;
428 case 0x01:
429 case 0x81:
430 refresh_clk = picos_to_clk(3900000);
431 break;
432 case 0x02:
433 case 0x82:
434 refresh_clk = picos_to_clk(7800000);
435 break;
436 case 0x03:
437 case 0x83:
438 refresh_clk = picos_to_clk(31300000);
439 break;
440 case 0x04:
441 case 0x84:
442 refresh_clk = picos_to_clk(62500000);
443 break;
444 case 0x05:
445 case 0x85:
446 refresh_clk = picos_to_clk(125000000);
447 break;
448 default:
449 refresh_clk = 0x512;
450 break;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500451 }
452
453 /*
454 * Set BSTOPRE to 0x100 for page mode
455 * If auto-charge is used, set BSTOPRE = 0
456 */
Dave Liu5f820432006-11-03 19:33:44 -0600457 ddr->sdram_interval = ((refresh_clk & 0x3fff) << 16) | 0x100;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500458 debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);
459
Dave Liuf6eda7f2006-10-25 14:41:21 -0500460 /* SS_EN = 0, source synchronous disable
461 * CLK_ADJST = 0, MCK/MCK# is launched aligned with addr/cmd
462 */
463 ddr->sdram_clk_cntl = 0x00000000;
464 debug("DDR:sdram_clk_cntl=0x%08x\n", ddr->sdram_clk_cntl);
Marian Balakowicz4c8d1ec2006-03-14 16:23:35 +0100465
Eran Libertyf046ccd2005-07-28 10:08:46 -0500466 asm("sync;isync");
467
Dave Liuf6eda7f2006-10-25 14:41:21 -0500468 udelay(600);
Eran Libertyf046ccd2005-07-28 10:08:46 -0500469
470 /*
Dave Liu5f820432006-11-03 19:33:44 -0600471 * Figure out the settings for the sdram_cfg register. Build up
472 * the value in 'sdram_cfg' before writing since the write into
Eran Libertyf046ccd2005-07-28 10:08:46 -0500473 * the register will actually enable the memory controller, and all
474 * settings must be done before enabling.
475 *
476 * sdram_cfg[0] = 1 (ddr sdram logic enable)
477 * sdram_cfg[1] = 1 (self-refresh-enable)
478 * sdram_cfg[6:7] = 2 (SDRAM type = DDR SDRAM)
Dave Liuf6eda7f2006-10-25 14:41:21 -0500479 * sdram_cfg[12] = 0 (32_BE =0 , 64 bit bus mode)
480 * sdram_cfg[13] = 0 (8_BE =0, 4-beat bursts)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500481 */
Dave Liuf6eda7f2006-10-25 14:41:21 -0500482 sdram_cfg = 0xC2000000;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500483
Dave Liuf6eda7f2006-10-25 14:41:21 -0500484 /* sdram_cfg[3] = RD_EN - registered DIMM enable */
485 if (spd.mod_attr & 0x02) {
486 sdram_cfg |= 0x10000000;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500487 }
488
Dave Liuf6eda7f2006-10-25 14:41:21 -0500489 /* The DIMM is 32bit width */
490 if (spd.dataw_lsb == 0x20) {
491 sdram_cfg |= 0x000C0000;
492 }
493 ddrc_ecc_enable = 0;
494
Eran Libertyf046ccd2005-07-28 10:08:46 -0500495#if defined(CONFIG_DDR_ECC)
Dave Liuf6eda7f2006-10-25 14:41:21 -0500496 /* Enable ECC with sdram_cfg[2] */
Eran Libertyf046ccd2005-07-28 10:08:46 -0500497 if (spd.config == 0x02) {
Dave Liuf6eda7f2006-10-25 14:41:21 -0500498 sdram_cfg |= 0x20000000;
499 ddrc_ecc_enable = 1;
500 /* disable error detection */
501 ddr->err_disable = ~ECC_ERROR_ENABLE;
502 /* set single bit error threshold to maximum value,
503 * reset counter to zero */
504 ddr->err_sbe = (255 << ECC_ERROR_MAN_SBET_SHIFT) |
Dave Liu5f820432006-11-03 19:33:44 -0600505 (0 << ECC_ERROR_MAN_SBEC_SHIFT);
Eran Libertyf046ccd2005-07-28 10:08:46 -0500506 }
Dave Liuf6eda7f2006-10-25 14:41:21 -0500507
508 debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
509 debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
Eran Libertyf046ccd2005-07-28 10:08:46 -0500510#endif
Dave Liu5f820432006-11-03 19:33:44 -0600511 printf(" DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF");
Eran Libertyf046ccd2005-07-28 10:08:46 -0500512
513#if defined(CONFIG_DDR_2T_TIMING)
514 /*
515 * Enable 2T timing by setting sdram_cfg[16].
516 */
Dave Liuf6eda7f2006-10-25 14:41:21 -0500517 sdram_cfg |= SDRAM_CFG_2T_EN;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500518#endif
Dave Liuf6eda7f2006-10-25 14:41:21 -0500519 /* Enable controller, and GO! */
520 ddr->sdram_cfg = sdram_cfg;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500521 asm("sync;isync");
522 udelay(500);
523
524 debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +0100525 return memsize; /*in MBytes*/
Eran Libertyf046ccd2005-07-28 10:08:46 -0500526}
Eran Libertyf046ccd2005-07-28 10:08:46 -0500527#endif /* CONFIG_SPD_EEPROM */
528
Dave Liuf6eda7f2006-10-25 14:41:21 -0500529#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500530/*
Marian Balakowicz4c8d1ec2006-03-14 16:23:35 +0100531 * Use timebase counter, get_timer() is not availabe
532 * at this point of initialization yet.
533 */
534static __inline__ unsigned long get_tbms (void)
535{
536 unsigned long tbl;
537 unsigned long tbu1, tbu2;
538 unsigned long ms;
539 unsigned long long tmp;
540
541 ulong tbclk = get_tbclk();
542
543 /* get the timebase ticks */
544 do {
545 asm volatile ("mftbu %0":"=r" (tbu1):);
546 asm volatile ("mftb %0":"=r" (tbl):);
547 asm volatile ("mftbu %0":"=r" (tbu2):);
548 } while (tbu1 != tbu2);
549
550 /* convert ticks to ms */
551 tmp = (unsigned long long)(tbu1);
552 tmp = (tmp << 32);
553 tmp += (unsigned long long)(tbl);
554 ms = tmp/(tbclk/1000);
555
556 return ms;
557}
558
559/*
Eran Libertyf046ccd2005-07-28 10:08:46 -0500560 * Initialize all of memory for ECC, then enable errors.
561 */
Wolfgang Denkcf48eb92006-04-16 10:51:58 +0200562/* #define CONFIG_DDR_ECC_INIT_VIA_DMA */
Marian Balakowicz4c8d1ec2006-03-14 16:23:35 +0100563void ddr_enable_ecc(unsigned int dram_size)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500564{
Eran Libertyf046ccd2005-07-28 10:08:46 -0500565 volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
Dave Liuf6eda7f2006-10-25 14:41:21 -0500566 volatile ddr83xx_t *ddr= &immap->ddr;
Marian Balakowicz4c8d1ec2006-03-14 16:23:35 +0100567 unsigned long t_start, t_end;
Dave Liu90f30a72006-11-02 18:05:50 -0600568 register u64 *p;
569 register uint size;
570 unsigned int pattern[2];
Marian Balakowicz4c8d1ec2006-03-14 16:23:35 +0100571#if defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
572 uint i;
573#endif
Marian Balakowicz4c8d1ec2006-03-14 16:23:35 +0100574 icache_enable();
Marian Balakowicz4c8d1ec2006-03-14 16:23:35 +0100575 t_start = get_tbms();
Dave Liu90f30a72006-11-02 18:05:50 -0600576 pattern[0] = 0xdeadbeef;
577 pattern[1] = 0xdeadbeef;
Marian Balakowicz4c8d1ec2006-03-14 16:23:35 +0100578
579#if !defined(CONFIG_DDR_ECC_INIT_VIA_DMA)
Dave Liu90f30a72006-11-02 18:05:50 -0600580 debug("ddr init: CPU FP write method\n");
581 size = dram_size;
582 for (p = 0; p < (u64*)(size); p++) {
583 ppcDWstore((u32*)p, pattern);
Eran Libertyf046ccd2005-07-28 10:08:46 -0500584 }
Dave Liu90f30a72006-11-02 18:05:50 -0600585 __asm__ __volatile__ ("sync");
Marian Balakowicz4c8d1ec2006-03-14 16:23:35 +0100586#else
Dave Liu90f30a72006-11-02 18:05:50 -0600587 debug("ddr init: DMA method\n");
588 size = 0x2000;
589 for (p = 0; p < (u64*)(size); p++) {
590 ppcDWstore((u32*)p, pattern);
Marian Balakowicz4c8d1ec2006-03-14 16:23:35 +0100591 }
Dave Liu90f30a72006-11-02 18:05:50 -0600592 __asm__ __volatile__ ("sync");
Eran Libertyf046ccd2005-07-28 10:08:46 -0500593
Dave Liu90f30a72006-11-02 18:05:50 -0600594 /* Initialise DMA for direct transfer */
595 dma_init();
596 /* Start DMA to transfer */
Dave Liu5f820432006-11-03 19:33:44 -0600597 dma_xfer((uint *)0x2000, 0x2000, (uint *)0); /* 8K */
598 dma_xfer((uint *)0x4000, 0x4000, (uint *)0); /* 16K */
599 dma_xfer((uint *)0x8000, 0x8000, (uint *)0); /* 32K */
600 dma_xfer((uint *)0x10000, 0x10000, (uint *)0); /* 64K */
601 dma_xfer((uint *)0x20000, 0x20000, (uint *)0); /* 128K */
602 dma_xfer((uint *)0x40000, 0x40000, (uint *)0); /* 256K */
603 dma_xfer((uint *)0x80000, 0x80000, (uint *)0); /* 512K */
604 dma_xfer((uint *)0x100000, 0x100000, (uint *)0); /* 1M */
605 dma_xfer((uint *)0x200000, 0x200000, (uint *)0); /* 2M */
606 dma_xfer((uint *)0x400000, 0x400000, (uint *)0); /* 4M */
Eran Libertyf046ccd2005-07-28 10:08:46 -0500607
608 for (i = 1; i < dram_size / 0x800000; i++) {
609 dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
610 }
Jon Loeligerde1d0a62005-08-01 13:20:47 -0500611#endif
Eran Libertyf046ccd2005-07-28 10:08:46 -0500612
Marian Balakowicz4c8d1ec2006-03-14 16:23:35 +0100613 t_end = get_tbms();
614 icache_disable();
615
616 debug("\nREADY!!\n");
617 debug("ddr init duration: %ld ms\n", t_end - t_start);
618
619 /* Clear All ECC Errors */
620 if ((ddr->err_detect & ECC_ERROR_DETECT_MME) == ECC_ERROR_DETECT_MME)
621 ddr->err_detect |= ECC_ERROR_DETECT_MME;
622 if ((ddr->err_detect & ECC_ERROR_DETECT_MBE) == ECC_ERROR_DETECT_MBE)
623 ddr->err_detect |= ECC_ERROR_DETECT_MBE;
624 if ((ddr->err_detect & ECC_ERROR_DETECT_SBE) == ECC_ERROR_DETECT_SBE)
625 ddr->err_detect |= ECC_ERROR_DETECT_SBE;
626 if ((ddr->err_detect & ECC_ERROR_DETECT_MSE) == ECC_ERROR_DETECT_MSE)
627 ddr->err_detect |= ECC_ERROR_DETECT_MSE;
628
629 /* Disable ECC-Interrupts */
630 ddr->err_int_en &= ECC_ERR_INT_DISABLE;
631
632 /* Enable errors for ECC */
633 ddr->err_disable &= ECC_ERROR_ENABLE;
634
635 __asm__ __volatile__ ("sync");
636 __asm__ __volatile__ ("isync");
637}
Eran Libertyf046ccd2005-07-28 10:08:46 -0500638#endif /* CONFIG_DDR_ECC */