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wdenke2211742002-11-02 23:30:20 +00001/*
2 * (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
3 *
4 * This file is based on similar values for other boards found in
5 * other U-Boot config files, mainly tqm8260.h and mpc8260ads.h.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26/*
27 * Config header file for a Interphase 4539 PMC, 64 MB SDRAM, 4MB Flash.
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
wdenke2211742002-11-02 23:30:20 +000033/*-----------------------------------------------------------------------
34 * High Level Configuration Options
35 * (easy to change)
36 */
37
38#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
39#define CONFIG_IPHASE4539 1 /* ...on a Interphase 4539 PMC */
40
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050041#define CONFIG_CPM2 1 /* Has a CPM2 */
42
wdenke2211742002-11-02 23:30:20 +000043/*-----------------------------------------------------------------------
44 * select serial console configuration
45 *
46 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
47 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
48 * for SCC).
49 *
50 * if CONFIG_CONS_NONE is defined, then the serial console routines must
51 * defined elsewhere (for example, on the cogent platform, there are serial
52 * ports on the motherboard which are used for the serial console - see
53 * cogent/cma101/serial.[ch]).
54 */
55#define CONFIG_CONS_ON_SMC /* define if console on SMC */
56#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
57#undef CONFIG_CONS_NONE /* define if console on something else */
58#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
59
60/*-----------------------------------------------------------------------
61 * select ethernet configuration
62 *
63 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
64 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
65 * for FCC)
66 *
67 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -050068 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenke2211742002-11-02 23:30:20 +000069 */
70#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
71#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
72#undef CONFIG_ETHER_NONE /* define if ether on something else */
73#define CONFIG_ETHER_INDEX 3 /* which channel for ether */
74
75#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
76
77/*-----------------------------------------------------------------------
78 * - Rx-CLK is CLK14
79 * - Tx-CLK is CLK16
80 * - Select bus for bd/buffers (see 28-13)
81 * - Half duplex
82 */
83# define CFG_CMXFCR_MASK (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
84# define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16)
85# define CFG_CPMFCR_RAMTYPE 0
86# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
87
88#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
89
90/* other options */
91
92#define CONFIG_8260_CLKIN 66666666 /* in Hz */
93#define CONFIG_BAUDRATE 19200
94
Jon Loeliger7be044e2007-07-09 21:24:19 -050095/*
96 * BOOTP options
97 */
98#define CONFIG_BOOTP_SUBNETMASK
99#define CONFIG_BOOTP_GATEWAY
100#define CONFIG_BOOTP_HOSTNAME
101#define CONFIG_BOOTP_BOOTPATH
102#define CONFIG_BOOTP_BOOTFILESIZE
wdenke2211742002-11-02 23:30:20 +0000103
104/*
105 * select i2c support configuration
106 *
107 * Supported configurations are {none, software, hardware} drivers.
108 * If the software driver is chosen, there are some additional
109 * configuration items that the driver uses to drive the port pins.
110 */
111#undef CONFIG_HARD_I2C /* I2C with hardware support */
112#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
113#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
114#define CFG_I2C_SLAVE 0x7F
115
116/*
117 * Software (bit-bang) I2C driver configuration
118 */
119#ifdef CONFIG_SOFT_I2C
120#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
121#define I2C_ACTIVE (iop->pdir |= 0x00010000)
122#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
123#define I2C_READ ((iop->pdat & 0x00010000) != 0)
124#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
125 else iop->pdat &= ~0x00010000
126#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
127 else iop->pdat &= ~0x00020000
128#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
129#endif /* CONFIG_SOFT_I2C */
130
wdenke2211742002-11-02 23:30:20 +0000131
Jon Loeliger348f2582007-07-08 13:46:18 -0500132/*
133 * Command line configuration.
134 */
135#include <config_cmd_default.h>
wdenke2211742002-11-02 23:30:20 +0000136
137
138#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
139#define CONFIG_BOOTCOMMAND "bootm 100000" /* autoboot command */
140#define CONFIG_BOOTARGS "root=/dev/ram rw"
141
Jon Loeliger348f2582007-07-08 13:46:18 -0500142#if defined(CONFIG_CMD_KGDB)
wdenke2211742002-11-02 23:30:20 +0000143#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
144#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
145#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
146#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
147#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
148#endif
149
150#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
151
152/*-----------------------------------------------------------------------
153 * Miscellaneous configurable options
154 */
155#define CFG_LONGHELP /* undef to save memory */
156#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger348f2582007-07-08 13:46:18 -0500157#if defined(CONFIG_CMD_KGDB)
wdenke2211742002-11-02 23:30:20 +0000158#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
159#else
160#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
161#endif
162#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
163#define CFG_MAXARGS 16 /* max number of command args */
164#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
165
166#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
167#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15 MB in DRAM */
168
169#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passed to Linux in MHz */
170 /* for versions < 2.4.5-pre5 */
171
172#define CFG_LOAD_ADDR 0x100000 /* default load address */
173
174#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
175
176#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
177
178#define CFG_RESET_ADDRESS 0x04400000
179
180#define CONFIG_MISC_INIT_R 1 /* We need misc_init_r() */
181
182/*-----------------------------------------------------------------------
183 * For booting Linux, the board info and command line data
184 * have to be in the first 8 MB of memory, since this is
185 * the maximum mapped by the Linux kernel during initialization.
186 */
187#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
188
189/*-----------------------------------------------------------------------
190 * Start addresses for the final memory configuration (Setup by the
191 * startup code). Please note that CFG_SDRAM_BASE _must_ start at 0.
192 */
193#define CFG_SDRAM_BASE 0x00000000
194#define CFG_FLASH_BASE 0xFF800000
195
196#define CFG_MONITOR_BASE TEXT_BASE
197#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
198#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
199
200/*-----------------------------------------------------------------------
201 * FLASH organization
202 */
203#define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */
204#define CFG_MAX_FLASH_SECT 64 /* max num of sects on one chip */
205#define CFG_MAX_FLASH_SIZE (CFG_MAX_FLASH_SECT * 0x10000) /* 4 MB */
206
207#define CFG_FLASH_ERASE_TOUT 2400000 /* Flash Erase Timeout (in ms) */
208#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
209
210/* Environment in FLASH, there is little space left in Serial EEPROM */
211#define CFG_ENV_IS_IN_FLASH 1
212#define CFG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */
213#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x10000) /* 2. sector */
214
215
216/*-----------------------------------------------------------------------
217 * Hard Reset Configuration Words
218 *
219 * if you change bits in the HRCW, you must also change the CFG_*
220 * defines for the various registers affected by the HRCW e.g. changing
221 * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
222 */
223#define CFG_HRCW_MASTER ( ( HRCW_BPS01 | HRCW_EBM ) |\
224 ( HRCW_L2CPC10 | HRCW_ISB110 ) |\
225 ( HRCW_MMR11 | HRCW_APPC10 ) |\
226 ( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \
227 ) /* 0x14863245 */
228
229/* no slaves */
230#define CFG_HRCW_SLAVE1 0
231#define CFG_HRCW_SLAVE2 0
232#define CFG_HRCW_SLAVE3 0
233#define CFG_HRCW_SLAVE4 0
234#define CFG_HRCW_SLAVE5 0
235#define CFG_HRCW_SLAVE6 0
236#define CFG_HRCW_SLAVE7 0
237
238/*-----------------------------------------------------------------------
239 * Internal Memory Mapped Register
240 */
241#define CFG_IMMR 0xFF000000 /* We keep original value */
242
243/*-----------------------------------------------------------------------
244 * Definitions for initial stack pointer and data area (in DPRAM)
245 */
246#define CFG_INIT_RAM_ADDR CFG_IMMR
247#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
248#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
249#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
250#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
251
252/*-----------------------------------------------------------------------
253 * Internal Definitions
254 *
255 * Boot Flags
256 */
257#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
258#define BOOTFLAG_WARM 0x02 /* Software reboot */
259
260
261/*-----------------------------------------------------------------------
262 * Cache Configuration
263 */
264#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
Jon Loeliger348f2582007-07-08 13:46:18 -0500265#if defined(CONFIG_CMD_KGDB)
wdenke2211742002-11-02 23:30:20 +0000266# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
267#endif
268
269/*-----------------------------------------------------------------------
270 * HIDx - Hardware Implementation-dependent Registers 2-11
271 *-----------------------------------------------------------------------
272 * HID0 also contains cache control.
273 *
274 * HID1 has only read-only information - nothing to set.
275 */
276#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200277 HID0_IFEM|HID0_ABE)
wdenke2211742002-11-02 23:30:20 +0000278#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE)
279#define CFG_HID2 0
280
281/*-----------------------------------------------------------------------
282 * RMR - Reset Mode Register 5-5
283 *-----------------------------------------------------------------------
284 * turn on Checkstop Reset Enable
285 */
286#define CFG_RMR RMR_CSRE
287
288/*-----------------------------------------------------------------------
289 * BCR - Bus Configuration 4-25
290 *-----------------------------------------------------------------------
291 */
292#define CFG_BCR 0xA01C0000
293
294/*-----------------------------------------------------------------------
295 * SIUMCR - SIU Module Configuration 4-31
296 *-----------------------------------------------------------------------
297 */
298#define CFG_SIUMCR 0X4205C000
299
300/*-----------------------------------------------------------------------
301 * SYPCR - System Protection Control 4-35
302 * SYPCR can only be written once after reset!
303 *-----------------------------------------------------------------------
304 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
305 */
306#if defined (CONFIG_WATCHDOG)
307#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
308 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
309#else
310#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
311 SYPCR_SWRI|SYPCR_SWP)
312#endif /* CONFIG_WATCHDOG */
313
314/*-----------------------------------------------------------------------
315 * TMCNTSC - Time Counter Status and Control 4-40
316 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
317 * and enable Time Counter
318 *-----------------------------------------------------------------------
319 */
320#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
321
322/*-----------------------------------------------------------------------
323 * PISCR - Periodic Interrupt Status and Control 4-42
324 *-----------------------------------------------------------------------
325 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
326 * Periodic timer
327 */
328#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
329
330/*-----------------------------------------------------------------------
331 * SCCR - System Clock Control 9-8
332 *-----------------------------------------------------------------------
333 * Ensure DFBRG is Divide by 16
334 */
335#define CFG_SCCR 0
336
337/*-----------------------------------------------------------------------
338 * RCCR - RISC Controller Configuration 13-7
339 *-----------------------------------------------------------------------
340 */
341#define CFG_RCCR 0
342
343/*-----------------------------------------------------------------------
344 * Init Memory Controller:
345 *
346 * Bank Bus Machine PortSz Device
347 * ---- --- ------- ------ ------
348 * 0 60x GPCM 64 bit FLASH
349 * 1 60x SDRAM 64 bit SDRAM
350 */
351
352#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) | 0x0801)
353#define CFG_OR0_PRELIM 0xFF800882
354#define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) | 0x0041)
355#define CFG_OR1_PRELIM 0xF8002CD0
356
357#define CFG_PSDMR 0x404A241A
358#define CFG_MPTPR 0x00007400
359#define CFG_PSRT 0x00000007
360
361#endif /* __CONFIG_H */