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Matthias Fuchs8ba132c2007-12-28 17:07:24 +01001/*
2 * (C) Copyright 2007
3 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com.
4 * Based on the sequoia configuration file.
5 *
6 * (C) Copyright 2006-2007
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
8 *
9 * (C) Copyright 2006
10 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
11 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29/************************************************************************
30 * PMC440.h - configuration for esd PMC440 boards
31 ***********************************************************************/
32#ifndef __CONFIG_H
33#define __CONFIG_H
34
35/*-----------------------------------------------------------------------
36 * High Level Configuration Options
37 *----------------------------------------------------------------------*/
38#define CONFIG_440EPX 1 /* Specific PPC440EPx */
39#define CONFIG_440 1 /* ... PPC440 family */
40#define CONFIG_4xx 1 /* ... PPC4xx family */
41
42#define CONFIG_SYS_CLK_FREQ 33333400
43
Matthias Fuchsff41ffc2008-01-11 14:55:16 +010044#if 0 /* temporary disabled because OS/9 does not like dcache on startup */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +010045#define CONFIG_4xx_DCACHE /* enable dcache */
Matthias Fuchsff41ffc2008-01-11 14:55:16 +010046#endif
Matthias Fuchs8ba132c2007-12-28 17:07:24 +010047
48#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
49#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
50#define CONFIG_BOARD_TYPES 1 /* support board types */
51/*-----------------------------------------------------------------------
52 * Base addresses -- Note these are effective addresses where the
53 * actual resources get mapped (not physical addresses)
54 *----------------------------------------------------------------------*/
55#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
56#define CFG_MALLOC_LEN (1024 * 1024) /* Reserve 256 kB for malloc() */
57
58#define CONFIG_PRAM 0 /* use pram variable to overwrite */
59
60#define CFG_BOOT_BASE_ADDR 0xf0000000
61#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
62#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
63#define CFG_MONITOR_BASE TEXT_BASE
64#define CFG_NAND_ADDR 0xd0000000 /* NAND Flash */
65#define CFG_OCM_BASE 0xe0010000 /* ocm */
66#define CFG_OCM_DATA_ADDR CFG_OCM_BASE
67#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
68#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
69#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
70#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
71#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
72#define CFG_PCI_MEMSIZE 0x80000000 /* 2GB! */
73
74/* Don't change either of these */
75#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
76
77#define CFG_USB2D0_BASE 0xe0000100
78#define CFG_USB_DEVICE 0xe0000000
79#define CFG_USB_HOST 0xe0000400
80#define CFG_FPGA_BASE0 0xef000000 /* 32 bit */
81#define CFG_FPGA_BASE1 0xef100000 /* 16 bit */
82
83/*-----------------------------------------------------------------------
84 * Initial RAM & stack pointer
85 *----------------------------------------------------------------------*/
86/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
87#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
88#define CFG_INIT_RAM_END (4 << 10)
89#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
90#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
91#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
92
93/*-----------------------------------------------------------------------
94 * Serial Port
95 *----------------------------------------------------------------------*/
96#undef CFG_EXT_SERIAL_CLOCK
97#define CONFIG_BAUDRATE 115200
98#define CONFIG_SERIAL_MULTI 1
99#undef CONFIG_UART1_CONSOLE /* console on front panel */
100
101#define CFG_BAUDRATE_TABLE \
102 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
103
104/*-----------------------------------------------------------------------
105 * Environment
106 *----------------------------------------------------------------------*/
107#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
108#define CFG_ENV_IS_IN_EEPROM 1 /* use FLASH for environment vars */
109#else
110#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
111#define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */
112#endif
113
114/*-----------------------------------------------------------------------
115 * RTC
116 *----------------------------------------------------------------------*/
117#define CONFIG_RTC_RX8025
118
119/*-----------------------------------------------------------------------
120 * FLASH related
121 *----------------------------------------------------------------------*/
122#define CFG_FLASH_CFI /* The flash is CFI compatible */
123#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
124
125#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
126
127#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
128#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
129
130#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
131#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
132
133#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
134#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
135
136#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
137#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
138
139#ifdef CFG_ENV_IS_IN_FLASH
140#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
141#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
142#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
143
144/* Address and size of Redundant Environment Sector */
145#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
146#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
147#endif
148
149#ifdef CFG_ENV_IS_IN_EEPROM
150#define CFG_ENV_OFFSET 0 /* environment starts at the beginning of the EEPROM */
151#define CFG_ENV_SIZE 0x1000 /* 4096 bytes may be used for env vars */
152#endif
153
154/*
155 * IPL (Initial Program Loader, integrated inside CPU)
156 * Will load first 4k from NAND (SPL) into cache and execute it from there.
157 *
158 * SPL (Secondary Program Loader)
159 * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
160 * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
161 * controller and the NAND controller so that the special U-Boot image can be
162 * loaded from NAND to SDRAM.
163 *
164 * NUB (NAND U-Boot)
165 * This NAND U-Boot (NUB) is a special U-Boot version which can be started
166 * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
167 *
168 * On 440EPx the SPL is copied to SDRAM before the NAND controller is
169 * set up. While still running from cache, I experienced problems accessing
170 * the NAND controller. sr - 2006-08-25
171 */
Matthias Fuchs7d5d7562008-01-08 11:13:09 +0100172#if defined (CONFIG_NAND_U_BOOT)
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100173#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
174#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
175#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_BASE + (12 << 10)) /* Copy SPL here */
176#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
177#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */
178#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
179
180/*
181 * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
182 */
183#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
184#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
185
186/*
187 * Now the NAND chip has to be defined (no autodetection used!)
188 */
189#define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */
190#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
191#define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */
192#define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
193#undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
194
195#define CFG_NAND_ECCSIZE 256
196#define CFG_NAND_ECCBYTES 3
197#define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
198#define CFG_NAND_OOBSIZE 16
199#define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
200#define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
Matthias Fuchs7d5d7562008-01-08 11:13:09 +0100201#endif
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100202
203#ifdef CFG_ENV_IS_IN_NAND
204/*
205 * For NAND booting the environment is embedded in the U-Boot image. Please take
206 * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
207 */
208#define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE
209#define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE)
210#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE)
211#endif
212
213/*-----------------------------------------------------------------------
214 * DDR SDRAM
215 *----------------------------------------------------------------------*/
216#define CFG_MBYTES_SDRAM (256) /* 256MB */
217#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
218#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
219#endif
220
221/*-----------------------------------------------------------------------
222 * I2C
223 *----------------------------------------------------------------------*/
224#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
225#undef CONFIG_SOFT_I2C /* I2C bit-banged */
226#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
227#define CFG_I2C_SLAVE 0x7F
228
229#define CONFIG_I2C_CMD_TREE 1
230#define CONFIG_I2C_MULTI_BUS 1
231
232#define CFG_I2C_MULTI_EEPROMS
233
234#define CFG_I2C_EEPROM_ADDR 0x54
235#define CFG_I2C_EEPROM_ADDR_LEN 2
236#define CFG_EEPROM_PAGE_WRITE_ENABLE
237#define CFG_EEPROM_PAGE_WRITE_BITS 5
238#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
239#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
240
241#define CFG_EEPROM_WREN 1
242#define CFG_I2C_BOOT_EEPROM_ADDR 0x52
243
244/*
245 * standard dtt sensor configuration - bottom bit will determine local or
246 * remote sensor of the TMP401
247 */
248#define CONFIG_DTT_SENSORS { 0, 1 }
249
250/*
251 * The PMC440 uses a TI TMP401 temperature sensor. This part
252 * is basically compatible to the ADM1021 that is supported
253 * by U-Boot.
254 *
255 * - i2c addr 0x4c
256 * - conversion rate 0x02 = 0.25 conversions/second
257 * - ALERT ouput disabled
258 * - local temp sensor enabled, min set to 0 deg, max set to 70 deg
259 * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
260 */
261#define CONFIG_DTT_ADM1021
262#define CFG_DTT_ADM1021 { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
263
264#define CONFIG_PREBOOT /* enable preboot variable */
265
266#undef CONFIG_BOOTARGS
267
268/* Setup some board specific values for the default environment variables */
269#define CONFIG_HOSTNAME pmc440
270#define CFG_BOOTFILE "bootfile=/tftpboot/pmc440/uImage\0"
271#define CFG_ROOTPATH "rootpath=/opt/eldk_410/ppc_4xx\0"
272
273#define CONFIG_EXTRA_ENV_SETTINGS \
274 CFG_BOOTFILE \
275 CFG_ROOTPATH \
276 "netdev=eth0\0" \
Matthias Fuchsff41ffc2008-01-11 14:55:16 +0100277 "ethrotate=no\0" \
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100278 "nfsargs=setenv bootargs root=/dev/nfs rw " \
279 "nfsroot=${serverip}:${rootpath}\0" \
280 "ramargs=setenv bootargs root=/dev/ram rw\0" \
281 "addip=setenv bootargs ${bootargs} " \
282 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
283 ":${hostname}:${netdev}:off panic=1\0" \
284 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
285 "flash_nfs=run nfsargs addip addtty;" \
286 "bootm ${kernel_addr}\0" \
287 "flash_self=run ramargs addip addtty;" \
288 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
289 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
290 "bootm\0" \
291 "kernel_addr=FC000000\0" \
292 "ramdisk_addr=FC180000\0" \
293 "load=tftp 200000 /tftpboot/pmc440/u-boot.bin\0" \
294 "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
295 "cp.b 200000 FFFA0000 60000\0" \
296 ""
297
298#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
299
300#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
301#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
302
303#define CONFIG_IBM_EMAC4_V4 1
304#define CONFIG_MII 1 /* MII PHY management */
305#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
306
307#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
308
309#define CONFIG_HAS_ETH0
310#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
311
312#define CONFIG_NET_MULTI 1
313#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
314#define CONFIG_PHY1_ADDR 1
315#define CONFIG_RESET_PHY_R 1
316
317/* USB */
318#define CONFIG_USB_OHCI_NEW
319#define CONFIG_USB_STORAGE
320#define CFG_OHCI_BE_CONTROLLER
321
322#define CFG_USB_OHCI_BOARD_INIT 1
323#define CFG_USB_OHCI_CPU_INIT 1
324#define CFG_USB_OHCI_REGS_BASE CFG_USB_HOST
325#define CFG_USB_OHCI_SLOT_NAME "ppc440"
326#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
327
328/* Comment this out to enable USB 1.1 device */
329#define USB_2_0_DEVICE
330
331/* Partitions */
332#define CONFIG_MAC_PARTITION
333#define CONFIG_DOS_PARTITION
334#define CONFIG_ISO_PARTITION
335
336#include <config_cmd_default.h>
337
338#define CONFIG_CMD_BSP
339#define CONFIG_CMD_DATE
340#define CONFIG_CMD_ASKENV
341#define CONFIG_CMD_DHCP
342#define CONFIG_CMD_DTT
343#define CONFIG_CMD_DIAG
344#define CONFIG_CMD_EEPROM
345#define CONFIG_CMD_ELF
346#define CONFIG_CMD_FAT
347#define CONFIG_CMD_I2C
348#define CONFIG_CMD_IRQ
349#define CONFIG_CMD_MII
350#define CONFIG_CMD_NAND
351#define CONFIG_CMD_NET
352#define CONFIG_CMD_NFS
353#define CONFIG_CMD_PCI
354#define CONFIG_CMD_PING
355#define CONFIG_CMD_USB
356#define CONFIG_CMD_REGINFO
357#define CONFIG_CMD_SDRAM
358
359/* POST support */
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100360#define CONFIG_POST (CFG_POST_MEMORY | \
361 CFG_POST_CPU | \
362 CFG_POST_UART | \
363 CFG_POST_I2C | \
364 CFG_POST_CACHE | \
365 CFG_POST_FPU | \
366 CFG_POST_ETHER | \
367 CFG_POST_SPR)
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100368
369#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
370
371/* esd expects pram at end of physical memory.
372 * So no logbuffer at the moment.
373 */
374#if 0
375#define CONFIG_LOGBUFFER
376#endif
377#define CFG_POST_CACHE_ADDR 0x10000000 /* free virtual address */
378
379#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
380
381#define CONFIG_SUPPORT_VFAT
382
383/*-----------------------------------------------------------------------
384 * Miscellaneous configurable options
385 *----------------------------------------------------------------------*/
386#define CFG_LONGHELP /* undef to save memory */
387#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Stefan Roesebe88b162008-01-17 07:50:17 +0100388#if defined(CONFIG_CMD_KGDB)
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100389#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
390#else
391#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
392#endif
393#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
394#define CFG_MAXARGS 16 /* max number of command args */
395#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
396
397#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
398#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
399
400#define CFG_LOAD_ADDR 0x100000 /* default load address */
401#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
402
403#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
404
405#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
406#define CONFIG_LOOPW 1 /* enable loopw command */
407#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
408#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
409#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
410
411#define CONFIG_AUTOBOOT_KEYED 1
412#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n"
413#undef CONFIG_AUTOBOOT_DELAY_STR
414#define CONFIG_AUTOBOOT_STOP_STR " "
415
416/*-----------------------------------------------------------------------
417 * PCI stuff
418 *----------------------------------------------------------------------*/
419/* General PCI */
420#define CONFIG_PCI /* include pci support */
421#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
422#define CFG_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
423#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
424#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
425
426/* Board-specific PCI */
427#define CFG_PCI_TARGET_INIT
428#define CFG_PCI_MASTER_INIT
429
430/* PCI identification */
431#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
432#define CFG_PCI_SUBSYS_ID_NONMONARCH 0x0441 /* PCI Device ID: Non-Monarch */
433#define CFG_PCI_SUBSYS_ID_MONARCH 0x0440 /* PCI Device ID: Monarch */
434#define CFG_PCI_CLASSCODE_NONMONARCH PCI_CLASS_PROCESSOR_POWERPC
435#define CFG_PCI_CLASSCODE_MONARCH PCI_CLASS_BRIDGE_HOST
436
437/*
438 * For booting Linux, the board info and command line data
439 * have to be in the first 8 MB of memory, since this is
440 * the maximum mapped by the Linux kernel during initialization.
441 */
442#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
443
444/*-----------------------------------------------------------------------
445 * FPGA stuff
446 *----------------------------------------------------------------------*/
447#define CONFIG_FPGA
448#define CONFIG_FPGA_XILINX
449#define CONFIG_FPGA_SPARTAN2
450#define CONFIG_FPGA_SPARTAN3
451
452#define CONFIG_FPGA_COUNT 2
453/*-----------------------------------------------------------------------
454 * External Bus Controller (EBC) Setup
455 *----------------------------------------------------------------------*/
456
457/*
458 * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
459 */
460#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
461#define CFG_NAND_CS 2 /* NAND chip connected to CSx */
462
463/* Memory Bank 0 (NOR-FLASH) initialization */
464#define CFG_EBC_PB0AP 0x03017200
465#define CFG_EBC_PB0CR (CFG_FLASH_BASE | 0xda000)
466
467/* Memory Bank 2 (NAND-FLASH) initialization */
468#define CFG_EBC_PB2AP 0x018003c0
469#define CFG_EBC_PB2CR (CFG_NAND_ADDR | 0x1c000)
470#else
471#define CFG_NAND_CS 0 /* NAND chip connected to CSx */
472/* Memory Bank 2 (NOR-FLASH) initialization */
473#define CFG_EBC_PB2AP 0x03017200
474#define CFG_EBC_PB2CR (CFG_FLASH_BASE | 0xda000)
475
476/* Memory Bank 0 (NAND-FLASH) initialization */
477#define CFG_EBC_PB0AP 0x018003c0
478#define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1c000)
479#endif
480
481/* Memory Bank 4 (FPGA / 32Bit) initialization */
482#define CFG_EBC_PB4AP 0x03840f40 /* BME=0,TWT=7,CSN=1,TH=7,RE=1,SOR=0,BEM=1 */
483#define CFG_EBC_PB4CR (CFG_FPGA_BASE0 | 0x1c000) /* BS=1M,BU=R/W,BW=32bit */
484
485/* Memory Bank 5 (FPGA / 16Bit) initialization */
486#define CFG_EBC_PB5AP 0x03840f40 /* BME=0,TWT=3,CSN=1,TH=0,RE=1,SOR=0,BEM=1 */
487#define CFG_EBC_PB5CR (CFG_FPGA_BASE1 | 0x1a000) /* BS=1M,BU=R/W,BW=16bit */
488
489/*-----------------------------------------------------------------------
490 * NAND FLASH
491 *----------------------------------------------------------------------*/
492#define CFG_MAX_NAND_DEVICE 1
493#define NAND_MAX_CHIPS 1
494#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
495#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
Matthias Fuchs7d5d7562008-01-08 11:13:09 +0100496#define CFG_NAND_QUIET_TEST 1
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100497
498/*
499 * Internal Definitions
500 *
501 * Boot Flags
502 */
503#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
504#define BOOTFLAG_WARM 0x02 /* Software reboot */
505
Stefan Roesebe88b162008-01-17 07:50:17 +0100506#if defined(CONFIG_CMD_KGDB)
Matthias Fuchs8ba132c2007-12-28 17:07:24 +0100507#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
508#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
509#endif
510
511/* pass open firmware flat tree */
512#define CONFIG_OF_LIBFDT 1
513#define CONFIG_OF_BOARD_SETUP 1
514
515#endif /* __CONFIG_H */