blob: da7d8b82b13198524f999948c0cb3dc45872d0b3 [file] [log] [blame]
wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2002
3 * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/* ------------------------------------------------------------------------- */
25
26/*
27 * board/config.h - configuration options, board specific
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
33/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37
38#define CONFIG_MPC824X 1
39#define CONFIG_MPC8240 1
40#define CONFIG_PN62 1
41
42#define CONFIG_CONS_INDEX 1
43
44
Jon Loeligeracf02692007-07-08 14:49:44 -050045/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -050046 * BOOTP options
47 */
48#define CONFIG_BOOTP_BOOTFILESIZE
49#define CONFIG_BOOTP_BOOTPATH
50#define CONFIG_BOOTP_GATEWAY
51#define CONFIG_BOOTP_HOSTNAME
52
53
54/*
Jon Loeligeracf02692007-07-08 14:49:44 -050055 * Command line configuration.
56 */
57#include <config_cmd_default.h>
wdenkc6097192002-11-03 00:24:07 +000058
Jon Loeligeracf02692007-07-08 14:49:44 -050059#define CONFIG_CMD_PCI
60#define CONFIG_CMD_BSP
61
62#undef CONFIG_CMD_AUTOSCRIPT
63#undef CONFIG_CMD_LOADS
64#undef CONFIG_CMD_ENV
65#undef CONFIG_CMD_FLASH
66#undef CONFIG_CMD_IMLS
67
wdenkc6097192002-11-03 00:24:07 +000068
69#define CONFIG_BAUDRATE 19200 /* console baudrate */
70
71#define CONFIG_BOOTDELAY 1 /* autoboot after n seconds */
72
73#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
74
75#define CONFIG_SERVERIP 10.0.0.201
Wolfgang Denk53677ef2008-05-20 16:00:29 +020076#define CONFIG_IPADDR 10.0.0.200
wdenkc6097192002-11-03 00:24:07 +000077#define CONFIG_ROOTPATH /opt/eldk/ppc_82xx
78#define CONFIG_NETMASK 255.255.255.0
79#undef CONFIG_BOOTARGS
80#if 0
81/* Boot Linux with NFS root filesystem */
82#define CONFIG_BOOTCOMMAND \
83 "setenv verify y;" \
Wolfgang Denk53677ef2008-05-20 16:00:29 +020084 "setenv bootargs console=ttyS0,19200 mem=31M quiet " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010085 "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
86 "ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \
wdenkc6097192002-11-03 00:24:07 +000087 "loadp 100000; bootm"
wdenk3bac3512003-03-12 10:41:04 +000088 /* "tftpboot 100000 uImage; bootm" */
wdenkc6097192002-11-03 00:24:07 +000089#else
90/* Boot Linux with RAMdisk based filesystem (initrd, BusyBox) */
91#define CONFIG_BOOTCOMMAND \
92 "setenv verify n;" \
Wolfgang Denk53677ef2008-05-20 16:00:29 +020093 "setenv bootargs console=ttyS0,19200 mem=31M quiet " \
wdenkc6097192002-11-03 00:24:07 +000094 "root=/dev/ram rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010095 "ip=${ipaddr}:${serverip}::${netmask}:pn62:eth0:off;" \
wdenkc6097192002-11-03 00:24:07 +000096 "loadp 200000; bootm"
97#endif
98
wdenkc6097192002-11-03 00:24:07 +000099/*
100 * Miscellaneous configurable options
101 */
102#define CFG_LONGHELP 1 /* undef to save memory */
103#define CFG_PROMPT "=> " /* Monitor Command Prompt */
104#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
105#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
106#define CFG_MAXARGS 16 /* max number of command args */
107#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
108#define CFG_LOAD_ADDR 0x00100000 /* default load address */
109#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
110
111#define CONFIG_PRAM 1024 /* reserve 1 MB protected RAM */
112
113#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() on init */
114
wdenke2ffd592004-12-31 09:32:47 +0000115#define CONFIG_HAS_ETH1 1 /* add support for eth1addr */
116
wdenkc6097192002-11-03 00:24:07 +0000117#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
118
119/*
120 * PCI stuff
121 */
122#define CONFIG_PCI /* include pci support */
123#define CONFIG_PCI_PNP /* we need Plug 'n Play */
124#if 0
125#define CONFIG_PCI_SCAN_SHOW /* show PCI auto-scan at boot */
126#endif
127
128/*
129 * Networking stuff
130 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200131#define CONFIG_NET_MULTI /* Multi ethernet cards support */
wdenkc6097192002-11-03 00:24:07 +0000132
133#define CONFIG_PCNET /* there are 2 AMD PCnet 79C973 */
134#define CONFIG_PCNET_79C973
135
136#define _IO_BASE 0xfe000000 /* points to PCI I/O space */
137
138
139/*
140 * Start addresses for the final memory configuration
141 * (Set up by the startup code)
142 * Please note that CFG_SDRAM_BASE _must_ start at 0
143 */
144#define CFG_SDRAM_BASE 0x00000000
145#define CFG_MAX_RAM_SIZE 0x10000000
146
147#define CFG_RESET_ADDRESS 0xfff00100
148
149#undef CFG_RAMBOOT
150#define CFG_MONITOR_LEN 0x00030000
151#define CFG_MONITOR_BASE TEXT_BASE
152
153/*#define CFG_GBL_DATA_SIZE 256*/
154#define CFG_GBL_DATA_SIZE 128
155
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200156#define CFG_INIT_RAM_ADDR 0x40000000
157#define CFG_INIT_RAM_END 0x1000
158#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
wdenkc6097192002-11-03 00:24:07 +0000159
160
161#define CFG_NO_FLASH 1 /* There is no FLASH memory */
162
163#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
164#define CFG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */
165#define CFG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */
166
167#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
168
169#define CFG_MEMTEST_START 0x00004000 /* memtest works on */
170#define CFG_MEMTEST_END 0x01f00000 /* 0 ... 32 MB in DRAM */
171
172/*
173 * Serial port configuration
174 */
175#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
176
177#define CFG_NS16550
178#define CFG_NS16550_SERIAL
179
180#define CFG_NS16550_REG_SIZE 1
181
182#define CFG_NS16550_CLK 1843200
183
184#define CFG_NS16550_COM1 0xff800008
185#define CFG_NS16550_COM2 0xff800000
186
187/*
188 * Low Level Configuration Settings
189 * (address mappings, register initial values, etc.)
190 * You should know what you are doing if you make changes here.
191 */
192
193#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
194#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3
195
196#define CFG_EUMB_ADDR 0xFCE00000
197
198/* MCCR1 */
199#define CFG_ROMNAL 3 /* rom/flash next access time */
200#define CFG_ROMFAL 7 /* rom/flash access time */
201
202/* MCCR2 */
203#define CFG_ASRISE 6 /* ASRISE in clocks */
204#define CFG_ASFALL 12 /* ASFALL in clocks */
205#define CFG_REFINT 5600 /* REFINT in clocks */
206
207/* MCCR3 */
208#define CFG_BSTOPRE 0x3cf /* Burst To Precharge */
209#define CFG_REFREC 2 /* Refresh to activate interval */
210#define CFG_RDLAT 3 /* data latency from read command */
211
212/* MCCR4 */
213#define CFG_PRETOACT 1 /* Precharge to activate interval */
214#define CFG_ACTTOPRE 3 /* Activate to Precharge interval */
215#define CFG_ACTORW 2 /* Activate to R/W */
216#define CFG_SDMODE_CAS_LAT 2 /* SDMODE CAS latency */
217#define CFG_SDMODE_WRAP 0 /* SDMODE Wrap type */
218#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */
219#define CFG_REGISTERD_TYPE_BUFFER 1
220
221/* Memory bank settings:
222 *
223 * only bits 20-29 are actually used from these vales to set the
224 * start/qend address the upper two bits will be 0, and the lower 20
225 * bits will be set to 0x00000 for a start address, or 0xfffff for an
226 * end address
227 */
228#define CFG_BANK0_START 0x00000000
229#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1)
230#define CFG_BANK0_ENABLE 1
231#define CFG_BANK1_START 0x00000000
232#define CFG_BANK1_END 0x00000000
233#define CFG_BANK1_ENABLE 0
234#define CFG_BANK2_START 0x00000000
235#define CFG_BANK2_END 0x00000000
236#define CFG_BANK2_ENABLE 0
237#define CFG_BANK3_START 0x00000000
238#define CFG_BANK3_END 0x00000000
239#define CFG_BANK3_ENABLE 0
240#define CFG_BANK4_START 0x00000000
241#define CFG_BANK4_END 0x00000000
242#define CFG_BANK4_ENABLE 0
243#define CFG_BANK5_START 0x00000000
244#define CFG_BANK5_END 0x00000000
245#define CFG_BANK5_ENABLE 0
246#define CFG_BANK6_START 0x00000000
247#define CFG_BANK6_END 0x00000000
248#define CFG_BANK6_ENABLE 0
249#define CFG_BANK7_START 0x00000000
250#define CFG_BANK7_END 0x00000000
251#define CFG_BANK7_ENABLE 0
252
253/*
254 * Memory bank enable bitmask, specifying which of the banks defined above
255 * are actually present. MSB is for bank #7, LSB is for bank #0.
256 */
257#define CFG_BANK_ENABLE 0x01
258
259#define CFG_ODCR 0xff /* configures line driver impedances, */
260 /* see 8240 book for bit definitions */
261#define CFG_PGMAX 0x32 /* how long the 8240 retains the */
262 /* currently accessed page in memory */
263 /* see 8240 book for details */
264
265/* SDRAM 0 - 256MB */
266#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
267#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
268
269#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
270#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
271
272/* PCI memory space */
273#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
274#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
275
276/* Config addrs, etc */
277#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
278#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
279
280#define CFG_DBAT0L CFG_IBAT0L
281#define CFG_DBAT0U CFG_IBAT0U
282#define CFG_DBAT1L CFG_IBAT1L
283#define CFG_DBAT1U CFG_IBAT1U
284#define CFG_DBAT2L CFG_IBAT2L
285#define CFG_DBAT2U CFG_IBAT2U
286#define CFG_DBAT3L CFG_IBAT3L
287#define CFG_DBAT3U CFG_IBAT3U
288
289/*
290 * For booting Linux, the board info and command line data
291 * have to be in the first 8 MB of memory, since this is
292 * the maximum mapped by the Linux kernel during initialization.
293 */
294#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
295
296/*
297 * Cache Configuration
298 */
299#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */
Jon Loeligeracf02692007-07-08 14:49:44 -0500300#if defined(CONFIG_CMD_KGDB)
wdenkc6097192002-11-03 00:24:07 +0000301# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
302#endif
303
304
305/*
306 * Internal Definitions
307 *
308 * Boot Flags
309 */
310#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
311#define BOOTFLAG_WARM 0x02 /* Software reboot */
312
313
314#endif /* __CONFIG_H */