| York Sun | d26e34c | 2016-12-28 08:43:40 -0800 | [diff] [blame^] | 1 | config SYS_FSL_DDR |
| 2 | bool |
| 3 | help |
| 4 | Select Freescale General DDR driver, shared between most Freescale |
| 5 | PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM- |
| 6 | based Layerscape SoCs (such as ls2080a). |
| 7 | |
| 8 | config SYS_FSL_MMDC |
| 9 | bool |
| 10 | help |
| 11 | Select Freescale Multi Mode DDR controller (MMDC). |
| 12 | |
| 13 | config SYS_FSL_DDR_BE |
| 14 | bool |
| 15 | help |
| 16 | Access DDR registers in big-endian |
| 17 | |
| 18 | config SYS_FSL_DDR_LE |
| 19 | bool |
| 20 | help |
| 21 | Access DDR registers in little-endian |
| 22 | |
| 23 | menu "Freescale DDR controllers" |
| 24 | depends on SYS_FSL_DDR |
| 25 | |
| 26 | config SYS_FSL_DDR_VER |
| 27 | int |
| 28 | default 50 if SYS_FSL_DDR_VER_50 |
| 29 | default 47 if SYS_FSL_DDR_VER_47 |
| 30 | default 46 if SYS_FSL_DDR_VER_46 |
| 31 | default 44 if SYS_FSL_DDR_VER_44 |
| 32 | |
| 33 | config SYS_FSL_DDR_VER_50 |
| 34 | bool |
| 35 | |
| 36 | config SYS_FSL_DDR_VER_47 |
| 37 | bool |
| 38 | |
| 39 | config SYS_FSL_DDR_VER_46 |
| 40 | bool |
| 41 | |
| 42 | config SYS_FSL_DDR_VER_44 |
| 43 | bool |
| 44 | |
| 45 | config SYS_FSL_DDRC_GEN1 |
| 46 | bool |
| 47 | help |
| 48 | Enable Freescale DDR controller. |
| 49 | |
| 50 | config SYS_FSL_DDRC_GEN2 |
| 51 | bool |
| 52 | depends on !MPC86xx |
| 53 | help |
| 54 | Enable Freescale DDR2 controller. |
| 55 | |
| 56 | config SYS_FSL_DDRC_86XX_GEN2 |
| 57 | bool |
| 58 | depends on MPC86xx |
| 59 | help |
| 60 | Enable Freescale DDR2 controller for MPC86xx SoCs. |
| 61 | |
| 62 | config SYS_FSL_DDRC_GEN3 |
| 63 | bool |
| 64 | depends on PPC |
| 65 | help |
| 66 | Enable Freescale DDR3 controller for PowerPC SoCs. |
| 67 | |
| 68 | config SYS_FSL_DDRC_ARM_GEN3 |
| 69 | bool |
| 70 | depends on ARM |
| 71 | help |
| 72 | Enable Freescale DDR3 controller for ARM SoCs. |
| 73 | |
| 74 | config SYS_FSL_DDRC_GEN4 |
| 75 | bool |
| 76 | help |
| 77 | Enable Freescale DDR4 controller. |
| 78 | |
| 79 | config SYS_FSL_HAS_DDR4 |
| 80 | bool |
| 81 | |
| 82 | config SYS_FSL_HAS_DDR3 |
| 83 | bool |
| 84 | |
| 85 | config SYS_FSL_HAS_DDR2 |
| 86 | bool |
| 87 | |
| 88 | config SYS_FSL_HAS_DDR1 |
| 89 | bool |
| 90 | |
| 91 | choice |
| 92 | prompt "DDR technology" |
| 93 | default SYS_FSL_DDR4 if SYS_FSL_HAS_DDR4 |
| 94 | default SYS_FSL_DDR3 if SYS_FSL_HAS_DDR3 |
| 95 | default SYS_FSL_DDR2 if SYS_FSL_HAS_DDR2 |
| 96 | default SYS_FSL_DDR1 if SYS_FSL_HAS_DDR1 |
| 97 | |
| 98 | config SYS_FSL_DDR4 |
| 99 | bool "Freescale DDR4 controller" |
| 100 | depends on SYS_FSL_HAS_DDR4 |
| 101 | select SYS_FSL_DDRC_GEN4 |
| 102 | |
| 103 | config SYS_FSL_DDR3 |
| 104 | bool "Freescale DDR3 controller" |
| 105 | depends on SYS_FSL_HAS_DDR3 |
| 106 | select SYS_FSL_DDRC_GEN3 if PPC |
| 107 | select SYS_FSL_DDRC_ARM_GEN3 if ARM |
| 108 | |
| 109 | config SYS_FSL_DDR2 |
| 110 | bool "Freescale DDR2 controller" |
| 111 | depends on SYS_FSL_HAS_DDR2 |
| 112 | select SYS_FSL_DDRC_GEN2 if (!MPC86xx && !SYS_FSL_DDRC_GEN3) |
| 113 | select SYS_FSL_DDRC_86XX_GEN2 if MPC86xx |
| 114 | |
| 115 | config SYS_FSL_DDR1 |
| 116 | bool "Freescale DDR1 controller" |
| 117 | depends on SYS_FSL_HAS_DDR1 |
| 118 | select SYS_FSL_DDRC_GEN1 |
| 119 | |
| 120 | endchoice |
| 121 | |
| 122 | endmenu |