Nobuhiro Iwamatsu | cff2f5f | 2014-06-26 10:23:30 +0900 | [diff] [blame] | 1 | /* |
| 2 | * include/configs/alt.h |
| 3 | * This file is alt board configuration. |
| 4 | * |
| 5 | * Copyright (C) 2014 Renesas Electronics Corporation |
| 6 | * |
| 7 | * SPDX-License-Identifier: GPL-2.0 |
| 8 | */ |
| 9 | |
| 10 | #ifndef __ALT_H |
| 11 | #define __ALT_H |
| 12 | |
| 13 | #undef DEBUG |
Nobuhiro Iwamatsu | 1cc95f6 | 2015-10-10 05:58:28 +0900 | [diff] [blame] | 14 | #define CONFIG_ARCH_RMOBILE_BOARD_STRING "Alt" |
Nobuhiro Iwamatsu | cff2f5f | 2014-06-26 10:23:30 +0900 | [diff] [blame] | 15 | |
Nobuhiro Iwamatsu | 5ca6dfe | 2014-11-10 14:34:07 +0900 | [diff] [blame] | 16 | #include "rcar-gen2-common.h" |
Nobuhiro Iwamatsu | cff2f5f | 2014-06-26 10:23:30 +0900 | [diff] [blame] | 17 | |
Nobuhiro Iwamatsu | 1cc95f6 | 2015-10-10 05:58:28 +0900 | [diff] [blame] | 18 | #if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT) |
Nobuhiro Iwamatsu | c9b59bf | 2014-10-31 16:16:28 +0900 | [diff] [blame] | 19 | #define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC |
| 20 | #else |
Nobuhiro Iwamatsu | cff2f5f | 2014-06-26 10:23:30 +0900 | [diff] [blame] | 21 | #define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC |
Nobuhiro Iwamatsu | c9b59bf | 2014-10-31 16:16:28 +0900 | [diff] [blame] | 22 | #endif |
Nobuhiro Iwamatsu | cff2f5f | 2014-06-26 10:23:30 +0900 | [diff] [blame] | 23 | #define STACK_AREA_SIZE 0xC000 |
| 24 | #define LOW_LEVEL_MERAM_STACK \ |
| 25 | (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) |
| 26 | |
| 27 | /* MEMORY */ |
Nobuhiro Iwamatsu | 5ca6dfe | 2014-11-10 14:34:07 +0900 | [diff] [blame] | 28 | #define RCAR_GEN2_SDRAM_BASE 0x40000000 |
| 29 | #define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) |
| 30 | #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) |
Nobuhiro Iwamatsu | cff2f5f | 2014-06-26 10:23:30 +0900 | [diff] [blame] | 31 | |
| 32 | /* SCIF */ |
Nobuhiro Iwamatsu | cff2f5f | 2014-06-26 10:23:30 +0900 | [diff] [blame] | 33 | |
| 34 | /* FLASH */ |
| 35 | #define CONFIG_SPI |
Nobuhiro Iwamatsu | cff2f5f | 2014-06-26 10:23:30 +0900 | [diff] [blame] | 36 | #define CONFIG_SPI_FLASH_QUAD |
Nobuhiro Iwamatsu | cff2f5f | 2014-06-26 10:23:30 +0900 | [diff] [blame] | 37 | |
Nobuhiro Iwamatsu | cff2f5f | 2014-06-26 10:23:30 +0900 | [diff] [blame] | 38 | /* SH Ether */ |
Nobuhiro Iwamatsu | cff2f5f | 2014-06-26 10:23:30 +0900 | [diff] [blame] | 39 | #define CONFIG_SH_ETHER_USE_PORT 0 |
| 40 | #define CONFIG_SH_ETHER_PHY_ADDR 0x1 |
| 41 | #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII |
| 42 | #define CONFIG_SH_ETHER_CACHE_WRITEBACK |
| 43 | #define CONFIG_SH_ETHER_CACHE_INVALIDATE |
| 44 | #define CONFIG_SH_ETHER_ALIGNE_SIZE 64 |
Nobuhiro Iwamatsu | cff2f5f | 2014-06-26 10:23:30 +0900 | [diff] [blame] | 45 | #define CONFIG_BITBANGMII |
| 46 | #define CONFIG_BITBANGMII_MULTI |
| 47 | |
| 48 | /* Board Clock */ |
| 49 | #define RMOBILE_XTAL_CLK 20000000u |
| 50 | #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK |
| 51 | #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ |
| 52 | #define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) |
| 53 | #define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24) |
Nobuhiro Iwamatsu | cff2f5f | 2014-06-26 10:23:30 +0900 | [diff] [blame] | 54 | |
| 55 | #define CONFIG_SYS_TMU_CLK_DIV 4 |
| 56 | |
| 57 | /* i2c */ |
Nobuhiro Iwamatsu | cff2f5f | 2014-06-26 10:23:30 +0900 | [diff] [blame] | 58 | #define CONFIG_SYS_I2C |
| 59 | #define CONFIG_SYS_I2C_SH |
| 60 | #define CONFIG_SYS_I2C_SLAVE 0x7F |
| 61 | #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3 |
Nobuhiro Iwamatsu | cff2f5f | 2014-06-26 10:23:30 +0900 | [diff] [blame] | 62 | #define CONFIG_SYS_I2C_SH_SPEED0 400000 |
Nobuhiro Iwamatsu | cff2f5f | 2014-06-26 10:23:30 +0900 | [diff] [blame] | 63 | #define CONFIG_SYS_I2C_SH_SPEED1 400000 |
Nobuhiro Iwamatsu | cff2f5f | 2014-06-26 10:23:30 +0900 | [diff] [blame] | 64 | #define CONFIG_SYS_I2C_SH_SPEED2 400000 |
| 65 | #define CONFIG_SH_I2C_DATA_HIGH 4 |
| 66 | #define CONFIG_SH_I2C_DATA_LOW 5 |
| 67 | #define CONFIG_SH_I2C_CLOCK 10000000 |
| 68 | |
| 69 | #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ |
| 70 | |
Nobuhiro Iwamatsu | 7ffc8df | 2014-10-31 16:30:26 +0900 | [diff] [blame] | 71 | /* USB */ |
Nobuhiro Iwamatsu | 7ffc8df | 2014-10-31 16:30:26 +0900 | [diff] [blame] | 72 | #define CONFIG_USB_EHCI_RMOBILE |
| 73 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 |
| 74 | |
Nobuhiro Iwamatsu | 2b8c081 | 2014-12-03 15:30:30 +0900 | [diff] [blame] | 75 | /* MMCIF */ |
Nobuhiro Iwamatsu | 2b8c081 | 2014-12-03 15:30:30 +0900 | [diff] [blame] | 76 | #define CONFIG_SH_MMCIF_ADDR 0xee200000 |
| 77 | #define CONFIG_SH_MMCIF_CLK 48000000 |
| 78 | |
Nobuhiro Iwamatsu | 8e2e588 | 2014-12-02 16:52:24 +0900 | [diff] [blame] | 79 | /* Module stop status bits */ |
| 80 | /* INTC-RT */ |
| 81 | #define CONFIG_SMSTP0_ENA 0x00400000 |
| 82 | /* MSIF */ |
| 83 | #define CONFIG_SMSTP2_ENA 0x00002000 |
| 84 | /* INTC-SYS, IRQC */ |
| 85 | #define CONFIG_SMSTP4_ENA 0x00000180 |
| 86 | /* SCIF2 */ |
| 87 | #define CONFIG_SMSTP7_ENA 0x00080000 |
| 88 | |
Nobuhiro Iwamatsu | 25f9613 | 2014-11-19 14:26:33 +0900 | [diff] [blame] | 89 | /* SDHI */ |
| 90 | #define CONFIG_SH_SDHI_FREQ 97500000 |
| 91 | |
Nobuhiro Iwamatsu | cff2f5f | 2014-06-26 10:23:30 +0900 | [diff] [blame] | 92 | #endif /* __ALT_H */ |