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Ben Whitten5aaef602017-11-23 13:47:47 +00001/*
2 * Configuation settings for the WB45N CPU Module.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef __CONFIG_H__
8#define __CONFIG_H__
9
10#include <asm/hardware.h>
11
Ben Whitten5aaef602017-11-23 13:47:47 +000012/* ARM asynchronous clock */
13#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
14#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
15
16#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
17#define CONFIG_SETUP_MEMORY_TAGS
18#define CONFIG_INITRD_TAG
19#define CONFIG_SKIP_LOWLEVEL_INIT
20
21/* general purpose I/O */
22#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
23#define CONFIG_AT91_GPIO
24
25/* serial console */
26#define CONFIG_ATMEL_USART
27#define CONFIG_USART_BASE ATMEL_BASE_DBGU
28#define CONFIG_USART_ID ATMEL_ID_SYS
29
30/*
31 * BOOTP options
32 */
33#define CONFIG_BOOTP_BOOTFILESIZE
Ben Whitten5aaef602017-11-23 13:47:47 +000034
35/* SDRAM */
36#define CONFIG_NR_DRAM_BANKS 1
37#define CONFIG_SYS_SDRAM_BASE 0x20000000
38#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 MB */
39
40#define CONFIG_SYS_INIT_SP_ADDR \
41 (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
42
43/* NAND flash */
44#define CONFIG_NAND_ATMEL
45#define CONFIG_SYS_MAX_NAND_DEVICE 1
46#define CONFIG_SYS_NAND_BASE 0x40000000
47/* our ALE is AD21 */
48#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
49/* our CLE is AD22 */
50#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
51#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
52#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
53
54/* PMECC & PMERRLOC */
55#define CONFIG_ATMEL_NAND_HWECC 1
56#define CONFIG_ATMEL_NAND_HW_PMECC 1
57#define CONFIG_PMECC_CAP 4
58#define CONFIG_PMECC_SECTOR_SIZE 512
59
60#define CONFIG_MTD_DEVICE
61#define CONFIG_CMD_MTDPARTS
62#define CONFIG_MTD_PARTITIONS
63#define CONFIG_RBTREE
64#define CONFIG_LZO
65
66/* Ethernet */
67#define CONFIG_MACB
68#define CONFIG_RMII
69#define CONFIG_NET_RETRY_COUNT 20
70#define CONFIG_MACB_SEARCH_PHY
71#define CONFIG_ETHADDR C0:EE:40:00:00:00
72#define CONFIG_ENV_OVERWRITE 1
73
74/* System */
75#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
76#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
77#define CONFIG_SYS_MEMTEST_END 0x23e00000
78
79#ifdef CONFIG_SYS_USE_NANDFLASH
80/* bootstrap + u-boot + env + linux in nandflash */
81#define CONFIG_ENV_OFFSET 0xa0000
82#define CONFIG_ENV_OFFSET_REDUND 0xc0000
83#define CONFIG_ENV_SIZE 0x20000 /* 1 block = 128 kB */
84
85#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xe0000 0x280000; " \
86 "run _mtd; bootm"
87
88#define MTDIDS_DEFAULT "nand0=atmel_nand"
89#define MTDPARTS_DEFAULT "mtdparts=atmel_nand:" \
90 "128K(at91bs)," \
91 "512K(u-boot)," \
92 "128K(u-boot-env)," \
93 "128K(redund-env)," \
94 "2560K(kernel-a)," \
95 "2560K(kernel-b)," \
96 "38912K(rootfs-a)," \
97 "38912K(rootfs-b)," \
98 "46208K(user)," \
99 "512K(logs)"
100
101#else
102#error No boot method selected, please select 'CONFIG_SYS_USE_NANDFLASH'
103#endif
104
105#define CONFIG_BOOTARGS "console=ttyS0,115200 earlyprintk " \
106 "rw noinitrd mem=64M " \
107 "rootfstype=ubifs root=ubi0:rootfs ubi.mtd=6"
108
109#define CONFIG_EXTRA_ENV_SETTINGS \
110 "_mtd=mtdparts default; setenv bootargs ${bootargs} ${mtdparts}\0" \
111 "autoload=no\0" \
112 "autostart=no\0" \
113 "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
114 "\0"
115
116#define CONFIG_SYS_CBSIZE 256
117#define CONFIG_SYS_MAXARGS 16
Ben Whitten5aaef602017-11-23 13:47:47 +0000118
119/*
120 * Size of malloc() pool
121 */
122#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000)
123
124/* SPL */
Ben Whitten5aaef602017-11-23 13:47:47 +0000125#define CONFIG_SPL_TEXT_BASE 0x300000
126#define CONFIG_SPL_MAX_SIZE 0x6000
127#define CONFIG_SPL_STACK 0x308000
128
129#define CONFIG_SPL_BSS_START_ADDR 0x20000000
130#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
131#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
132#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
133
134#define CONFIG_SYS_MONITOR_LEN (512 << 10)
135
136#define CONFIG_SYS_MASTER_CLOCK 132096000
137#define CONFIG_SYS_AT91_PLLA 0x20c73f03
138#define CONFIG_SYS_MCKR 0x1301
139#define CONFIG_SYS_MCKR_CSS 0x1302
140
141#define CONFIG_SPL_NAND_DRIVERS
142#define CONFIG_SPL_NAND_BASE
143#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
144#define CONFIG_SYS_NAND_5_ADDR_CYCLE
145#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
146#define CONFIG_SYS_NAND_PAGE_COUNT 64
147#define CONFIG_SYS_NAND_OOBSIZE 64
148#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
149#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
150#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
151
152#endif /* __CONFIG_H__ */