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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / d3b7ff14f4944a391da3d1146e36dba42e811766 / . / test / dm / test.dts
blob: 96775e10ba0c396fff52ee6497a6c427ddb479da [file] [log] [blame]
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]1/dts-v1/;
2
3/ {
4 model = "sandbox";
5 compatible = "sandbox";
6 #address-cells = <1>;
7 #size-cells = <0>;
8
Simon Glass00606d72014-07-23 06:55:03 -0600[diff] [blame]9 aliases {
10 console = &uart0;
Simon Glass9cc36a22015-01-25 08:27:05 -0700[diff] [blame]11 i2c0 = "/i2c@0";
12 spi0 = "/spi@0";
Simon Glassd3b7ff12015-03-05 12:25:34 -0700[diff] [blame^]13 pci0 = &pci;
Simon Glass5a66a8f2014-07-23 06:55:12 -0600[diff] [blame]14 testfdt6 = "/e-test";
Simon Glass9cc36a22015-01-25 08:27:05 -0700[diff] [blame]15 testbus3 = "/some-bus";
16 testfdt0 = "/some-bus/c-test@0";
17 testfdt1 = "/some-bus/c-test@1";
18 testfdt3 = "/b-test";
19 testfdt5 = "/some-bus/c-test@5";
20 testfdt8 = "/a-test";
Simon Glass00606d72014-07-23 06:55:03 -0600[diff] [blame]21 };
22
23 uart0: serial {
24 compatible = "sandbox,serial";
25 u-boot,dm-pre-reloc;
26 };
27
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]28 a-test {
29 reg = <0>;
30 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]31 ping-expect = <0>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]32 ping-add = <0>;
Simon Glass00606d72014-07-23 06:55:03 -0600[diff] [blame]33 u-boot,dm-pre-reloc;
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]34 test-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 5 0 3 2 1>,
35 <0>, <&gpio_a 12>;
36 test2-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 6 1 3 2 1>,
37 <&gpio_b 7 2 3 2 1>, <&gpio_b 8 4 3 2 1>,
38 <&gpio_b 9 0xc 3 2 1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]39 };
40
41 junk {
42 reg = <1>;
43 compatible = "not,compatible";
44 };
45
46 no-compatible {
47 reg = <2>;
48 };
49
50 b-test {
51 reg = <3>;
52 compatible = "denx,u-boot-fdt-test";
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]53 ping-expect = <3>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]54 ping-add = <3>;
55 };
56
57 some-bus {
58 #address-cells = <1>;
59 #size-cells = <0>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]60 compatible = "denx,u-boot-test-bus";
Simon Glass5a66a8f2014-07-23 06:55:12 -0600[diff] [blame]61 reg = <3>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]62 ping-expect = <4>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]63 ping-add = <4>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]64 c-test@5 {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]65 compatible = "denx,u-boot-fdt-test";
66 reg = <5>;
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]67 ping-expect = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]68 ping-add = <5>;
69 };
Simon Glass1ca7e202014-07-23 06:55:18 -0600[diff] [blame]70 c-test@0 {
71 compatible = "denx,u-boot-fdt-test";
72 reg = <0>;
73 ping-expect = <6>;
74 ping-add = <6>;
75 };
76 c-test@1 {
77 compatible = "denx,u-boot-fdt-test";
78 reg = <1>;
79 ping-expect = <7>;
80 ping-add = <7>;
81 };
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]82 };
83
84 d-test {
Simon Glass5a66a8f2014-07-23 06:55:12 -0600[diff] [blame]85 reg = <3>;
86 ping-expect = <6>;
87 ping-add = <6>;
88 compatible = "google,another-fdt-test";
89 };
90
91 e-test {
92 reg = <3>;
Simon Glasseb9ef5f2014-07-23 06:54:57 -0600[diff] [blame]93 ping-expect = <6>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]94 ping-add = <6>;
95 compatible = "google,another-fdt-test";
96 };
97
Simon Glass9cc36a22015-01-25 08:27:05 -0700[diff] [blame]98 f-test {
99 compatible = "denx,u-boot-fdt-test";
100 };
101
102 g-test {
103 compatible = "denx,u-boot-fdt-test";
104 };
105
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]106 gpio_a: base-gpios {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]107 compatible = "sandbox,gpio";
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]108 gpio-controller;
109 #gpio-cells = <1>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]110 gpio-bank-name = "a";
111 num-gpios = <20>;
112 };
113
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]114 gpio_b: extra-gpios {
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]115 compatible = "sandbox,gpio";
Simon Glass3669e0e2015-01-05 20:05:29 -0700[diff] [blame]116 gpio-controller;
117 #gpio-cells = <5>;
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]118 gpio-bank-name = "b";
119 num-gpios = <10>;
120 };
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]121
Simon Glassecc2ed52014-12-10 08:55:55 -0700[diff] [blame]122 i2c@0 {
123 #address-cells = <1>;
124 #size-cells = <0>;
125 reg = <0>;
126 compatible = "sandbox,i2c";
127 clock-frequency = <100000>;
128 eeprom@2c {
129 reg = <0x2c>;
130 compatible = "i2c-eeprom";
131 emul {
132 compatible = "sandbox,i2c-eeprom";
133 sandbox,filename = "i2c.bin";
134 sandbox,size = <256>;
135 };
136 };
137 };
138
Simon Glassd3b7ff12015-03-05 12:25:34 -0700[diff] [blame^]139 pci: pci-controller {
140 compatible = "sandbox,pci";
141 device_type = "pci";
142 #address-cells = <3>;
143 #size-cells = <2>;
144 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000
145 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
146 pci@1f,0 {
147 compatible = "pci-generic";
148 reg = <0xf800 0 0 0 0>;
149 emul@1f,0 {
150 compatible = "sandbox,swap-case";
151 };
152 };
153 };
154
Simon Glass0ae0cb72014-10-13 23:42:11 -0600[diff] [blame]155 spi@0 {
156 #address-cells = <1>;
157 #size-cells = <0>;
158 reg = <0>;
159 compatible = "sandbox,spi";
160 cs-gpios = <0>, <&gpio_a 0>;
161 spi.bin@0 {
162 reg = <0>;
163 compatible = "spansion,m25p16", "spi-flash";
164 spi-max-frequency = <40000000>;
165 sandbox,filename = "spi.bin";
166 };
167 };
168
Simon Glass2e7d35d2014-02-26 15:59:21 -0700[diff] [blame]169};