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wdenk3d3befa2004-03-14 15:06:13 +00001/*
2 * (C) Copyright 2003, 2004
3 * ARM Ltd.
4 * Philippe Robin, <philippe.robin@arm.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25/*
wdenk42dfe7a2004-03-14 22:25:36 +000026 * ARM PrimeCell UART's (PL010 & PL011)
wdenk3d3befa2004-03-14 15:06:13 +000027 * ------------------------------------
wdenk42dfe7a2004-03-14 22:25:36 +000028 *
wdenk3d3befa2004-03-14 15:06:13 +000029 * Definitions common to both PL010 & PL011
wdenk42dfe7a2004-03-14 22:25:36 +000030 *
wdenk3d3befa2004-03-14 15:06:13 +000031 */
Rabin Vincent72d5e442010-05-05 09:23:07 +053032
33#ifndef __ASSEMBLY__
34/*
35 * We can use a combined structure for PL010 and PL011, because they overlap
36 * only in common registers.
37 */
38struct pl01x_regs {
39 u32 dr; /* 0x00 Data register */
40 u32 ecr; /* 0x04 Error clear register (Write) */
41 u32 pl010_lcrh; /* 0x08 Line control register, high byte */
42 u32 pl010_lcrm; /* 0x0C Line control register, middle byte */
43 u32 pl010_lcrl; /* 0x10 Line control register, low byte */
44 u32 pl010_cr; /* 0x14 Control register */
45 u32 fr; /* 0x18 Flag register (Read only) */
John Rigby910f1ae2011-04-19 10:42:39 +000046#ifdef CONFIG_PL011_SERIAL_RLCR
47 u32 pl011_rlcr; /* 0x1c Receive line control register */
48#else
Rabin Vincent72d5e442010-05-05 09:23:07 +053049 u32 reserved;
John Rigby910f1ae2011-04-19 10:42:39 +000050#endif
Rabin Vincent72d5e442010-05-05 09:23:07 +053051 u32 ilpr; /* 0x20 IrDA low-power counter register */
52 u32 pl011_ibrd; /* 0x24 Integer baud rate register */
53 u32 pl011_fbrd; /* 0x28 Fractional baud rate register */
54 u32 pl011_lcrh; /* 0x2C Line control register */
55 u32 pl011_cr; /* 0x30 Control register */
56};
57#endif
wdenk3d3befa2004-03-14 15:06:13 +000058
59#define UART_PL01x_RSR_OE 0x08
60#define UART_PL01x_RSR_BE 0x04
61#define UART_PL01x_RSR_PE 0x02
62#define UART_PL01x_RSR_FE 0x01
63
64#define UART_PL01x_FR_TXFE 0x80
65#define UART_PL01x_FR_RXFF 0x40
66#define UART_PL01x_FR_TXFF 0x20
67#define UART_PL01x_FR_RXFE 0x10
68#define UART_PL01x_FR_BUSY 0x08
69#define UART_PL01x_FR_TMSK (UART_PL01x_FR_TXFF + UART_PL01x_FR_BUSY)
70
wdenk42dfe7a2004-03-14 22:25:36 +000071/*
wdenk3d3befa2004-03-14 15:06:13 +000072 * PL010 definitions
wdenk42dfe7a2004-03-14 22:25:36 +000073 *
wdenk3d3befa2004-03-14 15:06:13 +000074 */
wdenk3d3befa2004-03-14 15:06:13 +000075#define UART_PL010_CR_LPE (1 << 7)
76#define UART_PL010_CR_RTIE (1 << 6)
77#define UART_PL010_CR_TIE (1 << 5)
78#define UART_PL010_CR_RIE (1 << 4)
79#define UART_PL010_CR_MSIE (1 << 3)
80#define UART_PL010_CR_IIRLP (1 << 2)
81#define UART_PL010_CR_SIREN (1 << 1)
82#define UART_PL010_CR_UARTEN (1 << 0)
wdenk42dfe7a2004-03-14 22:25:36 +000083
wdenk3d3befa2004-03-14 15:06:13 +000084#define UART_PL010_LCRH_WLEN_8 (3 << 5)
85#define UART_PL010_LCRH_WLEN_7 (2 << 5)
86#define UART_PL010_LCRH_WLEN_6 (1 << 5)
87#define UART_PL010_LCRH_WLEN_5 (0 << 5)
88#define UART_PL010_LCRH_FEN (1 << 4)
89#define UART_PL010_LCRH_STP2 (1 << 3)
90#define UART_PL010_LCRH_EPS (1 << 2)
91#define UART_PL010_LCRH_PEN (1 << 1)
92#define UART_PL010_LCRH_BRK (1 << 0)
93
94
95#define UART_PL010_BAUD_460800 1
96#define UART_PL010_BAUD_230400 3
97#define UART_PL010_BAUD_115200 7
98#define UART_PL010_BAUD_57600 15
99#define UART_PL010_BAUD_38400 23
100#define UART_PL010_BAUD_19200 47
101#define UART_PL010_BAUD_14400 63
102#define UART_PL010_BAUD_9600 95
103#define UART_PL010_BAUD_4800 191
104#define UART_PL010_BAUD_2400 383
105#define UART_PL010_BAUD_1200 767
wdenk42dfe7a2004-03-14 22:25:36 +0000106/*
wdenk3d3befa2004-03-14 15:06:13 +0000107 * PL011 definitions
wdenk42dfe7a2004-03-14 22:25:36 +0000108 *
wdenk3d3befa2004-03-14 15:06:13 +0000109 */
wdenk3d3befa2004-03-14 15:06:13 +0000110#define UART_PL011_LCRH_SPS (1 << 7)
111#define UART_PL011_LCRH_WLEN_8 (3 << 5)
112#define UART_PL011_LCRH_WLEN_7 (2 << 5)
113#define UART_PL011_LCRH_WLEN_6 (1 << 5)
114#define UART_PL011_LCRH_WLEN_5 (0 << 5)
115#define UART_PL011_LCRH_FEN (1 << 4)
116#define UART_PL011_LCRH_STP2 (1 << 3)
117#define UART_PL011_LCRH_EPS (1 << 2)
118#define UART_PL011_LCRH_PEN (1 << 1)
119#define UART_PL011_LCRH_BRK (1 << 0)
120
121#define UART_PL011_CR_CTSEN (1 << 15)
122#define UART_PL011_CR_RTSEN (1 << 14)
123#define UART_PL011_CR_OUT2 (1 << 13)
124#define UART_PL011_CR_OUT1 (1 << 12)
125#define UART_PL011_CR_RTS (1 << 11)
126#define UART_PL011_CR_DTR (1 << 10)
127#define UART_PL011_CR_RXE (1 << 9)
128#define UART_PL011_CR_TXE (1 << 8)
129#define UART_PL011_CR_LPE (1 << 7)
130#define UART_PL011_CR_IIRLP (1 << 2)
131#define UART_PL011_CR_SIREN (1 << 1)
132#define UART_PL011_CR_UARTEN (1 << 0)
133
134#define UART_PL011_IMSC_OEIM (1 << 10)
135#define UART_PL011_IMSC_BEIM (1 << 9)
136#define UART_PL011_IMSC_PEIM (1 << 8)
137#define UART_PL011_IMSC_FEIM (1 << 7)
138#define UART_PL011_IMSC_RTIM (1 << 6)
139#define UART_PL011_IMSC_TXIM (1 << 5)
140#define UART_PL011_IMSC_RXIM (1 << 4)
141#define UART_PL011_IMSC_DSRMIM (1 << 3)
142#define UART_PL011_IMSC_DCDMIM (1 << 2)
143#define UART_PL011_IMSC_CTSMIM (1 << 1)
144#define UART_PL011_IMSC_RIMIM (1 << 0)