blob: 7f2b842993555bed99fc5faf01c68bae0f92f571 [file] [log] [blame]
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +01001/*
2 * (C) Copyright 2000-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2006
6 * Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +01009 */
10
11/*
12 * board/config.h - configuration options, board specific
13 */
14
15#ifndef __CONFIG_H
16#define __CONFIG_H
17
18/*
19 * High Level Configuration Options
20 * (easy to change)
21 */
22
23#define CONFIG_MPC885 1 /* This is a MPC885 CPU */
24#define CONFIG_TQM885D 1 /* ...on a TQM88D module */
25#define CONFIG_TK885D 1 /* ...in a TK885D base board */
26
Wolfgang Denk2ae18242010-10-06 09:05:45 +020027#define CONFIG_SYS_TEXT_BASE 0x40000000
28
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +010029#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020030#define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */
31#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +010032#define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 66 MHz - CPU default clock */
33 /* (it will be used if there is no */
34 /* 'cpuclk' variable with valid value) */
35
36#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
Wolfgang Denk3cb7a482009-07-28 22:13:52 +020037#define CONFIG_SYS_SMC_RXBUFLEN 128
38#define CONFIG_SYS_MAXIDLE 10
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +010039#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
40
41#define CONFIG_BOOTCOUNT_LIMIT
42
43#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
44
45#define CONFIG_BOARD_TYPES 1 /* support board types */
46
47#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010048 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +010049 "echo"
50
51#undef CONFIG_BOOTARGS
52
53#define CONFIG_EXTRA_ENV_SETTINGS \
Heiko Schocher48690d82010-07-20 17:45:02 +020054 "ethprime=FEC\0" \
55 "ethact=FEC\0" \
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +010056 "netdev=eth0\0" \
57 "nfsargs=setenv bootargs root=/dev/nfs rw " \
58 "nfsroot=${serverip}:${rootpath}\0" \
59 "ramargs=setenv bootargs root=/dev/ram rw\0" \
60 "addip=setenv bootargs ${bootargs} " \
61 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
62 ":${hostname}:${netdev}:off panic=1\0" \
63 "flash_nfs=run nfsargs addip;" \
64 "bootm ${kernel_addr}\0" \
65 "flash_self=run ramargs addip;" \
66 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
67 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
68 "rootpath=/opt/eldk/ppc_8xx\0" \
Wolfgang Denk2b4f7782008-01-15 17:21:28 +010069 "bootfile=/tftpboot/tk885d/uImage\0" \
70 "u-boot=/tftpboot/tk885d/u-boot.bin\0" \
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +010071 "kernel_addr=40080000\0" \
72 "ramdisk_addr=40180000\0" \
73 "load=tftp 200000 ${u-boot}\0" \
74 "update=protect off 40000000 +${filesize};" \
75 "erase 40000000 +${filesize};" \
76 "cp.b 200000 40000000 ${filesize};" \
77 "protect on 40000000 +${filesize}\0" \
78 ""
79#define CONFIG_BOOTCOMMAND "run flash_self"
80
81#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020082#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +010083
84#undef CONFIG_WATCHDOG /* watchdog disabled */
85
86#define CONFIG_STATUS_LED 1 /* Status LED enabled */
87
88#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
89
90/* enable I2C and select the hardware/software driver */
Heiko Schocherea818db2013-01-29 08:53:15 +010091#define CONFIG_SYS_I2C
92#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
93#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */
94#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +010095/*
96 * Software (bit-bang) I2C driver configuration
97 */
98#define PB_SCL 0x00000020 /* PB 26 */
99#define PB_SDA 0x00000010 /* PB 27 */
100
101#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
102#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
103#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
104#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
105#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
106 else immr->im_cpm.cp_pbdat &= ~PB_SDA
107#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
108 else immr->im_cpm.cp_pbdat &= ~PB_SCL
109#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100110
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C?? */
112#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
113#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
114#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100115
116# define CONFIG_RTC_DS1337 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117# define CONFIG_SYS_I2C_RTC_ADDR 0x68
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100118
119/*
120 * BOOTP options
121 */
122#define CONFIG_BOOTP_SUBNETMASK
123#define CONFIG_BOOTP_GATEWAY
124#define CONFIG_BOOTP_HOSTNAME
125#define CONFIG_BOOTP_BOOTPATH
126#define CONFIG_BOOTP_BOOTFILESIZE
127
128
129#define CONFIG_MAC_PARTITION
130#define CONFIG_DOS_PARTITION
131
132#undef CONFIG_RTC_MPC8xx /* MPC885 does not support RTC */
133
134#define CONFIG_TIMESTAMP /* but print image timestmps */
135
136
137/*
138 * Command line configuration.
139 */
140#include <config_cmd_default.h>
141
142#define CONFIG_CMD_ASKENV
143#define CONFIG_CMD_DATE
144#define CONFIG_CMD_DHCP
145#define CONFIG_CMD_EEPROM
146#define CONFIG_CMD_I2C
147#define CONFIG_CMD_IDE
148#define CONFIG_CMD_MII
149#define CONFIG_CMD_NFS
150#define CONFIG_CMD_PING
151
152
153/*
154 * Miscellaneous configurable options
155 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_LONGHELP /* undef to save memory */
157#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100158
159#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100161
162#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100164#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100166#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
168#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
169#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100170
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
172#define CONFIG_SYS_MEMTEST_END 0x0300000 /* 1 ... 3 MB in DRAM */
173#define CONFIG_SYS_ALT_MEMTEST /* alternate, more extensive
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100174 memory test.*/
175
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100177
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100179
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100180/*
181 * Enable loopw command.
182 */
183#define CONFIG_LOOPW
184
185/*
186 * Low Level Configuration Settings
187 * (address mappings, register initial values, etc.)
188 * You should know what you are doing if you make changes here.
189 */
190/*-----------------------------------------------------------------------
191 * Internal Memory Mapped Register
192 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_IMMR 0xFFF00000
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100194
195/*-----------------------------------------------------------------------
196 * Definitions for initial stack pointer and data area (in DPRAM)
197 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200199#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200200#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100202
203/*-----------------------------------------------------------------------
204 * Start addresses for the final memory configuration
205 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100207 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_SDRAM_BASE 0x00000000
209#define CONFIG_SYS_FLASH_BASE 0x40000000
210#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
211#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
212#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100213
214/*
215 * For booting Linux, the board info and command line data
216 * have to be in the first 8 MB of memory, since this is
217 * the maximum mapped by the Linux kernel during initialization.
218 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100220
221/*-----------------------------------------------------------------------
222 * FLASH organization
223 */
224
225/* use CFI flash driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200227#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
229#define CONFIG_SYS_FLASH_EMPTY_INFO
230#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
231#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
232#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100233
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200234#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200235#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
236#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */
237#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100238
239/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200240#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
241#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100242
243/*-----------------------------------------------------------------------
244 * Hardware Information Block
245 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
247#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
248#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100249
250/*-----------------------------------------------------------------------
251 * Cache Configuration
252 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100254#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100256#endif
257
258/*-----------------------------------------------------------------------
259 * SYPCR - System Protection Control 11-9
260 * SYPCR can only be written once after reset!
261 *-----------------------------------------------------------------------
262 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
263 */
264#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100266 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
267#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100269#endif
270
271/*-----------------------------------------------------------------------
272 * SIUMCR - SIU Module Configuration 11-6
273 *-----------------------------------------------------------------------
274 * PCMCIA config., multi-function pin tri-state
275 */
276#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100278#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100280#endif /* CONFIG_CAN_DRIVER */
281
282/*-----------------------------------------------------------------------
283 * TBSCR - Time Base Status and Control 11-26
284 *-----------------------------------------------------------------------
285 * Clear Reference Interrupt Status, Timebase freezing enabled
286 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100288
289/*-----------------------------------------------------------------------
290 * PISCR - Periodic Interrupt Status and Control 11-31
291 *-----------------------------------------------------------------------
292 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
293 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100295
296/*-----------------------------------------------------------------------
297 * SCCR - System Clock and reset Control Register 15-27
298 *-----------------------------------------------------------------------
299 * Set clock output, timebase and RTC source and divider,
300 * power management and some other internal clocks
301 */
302#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100304 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
305 SCCR_DFALCD00)
306
307/*-----------------------------------------------------------------------
308 * PCMCIA stuff
309 *-----------------------------------------------------------------------
310 *
311 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
313#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
314#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
315#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
316#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
317#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
318#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
319#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100320
321/*-----------------------------------------------------------------------
322 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
323 *-----------------------------------------------------------------------
324 */
325
Pavel Herrmann8d1165e11a2012-10-09 07:01:56 +0000326#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100327#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
328
329#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
330#undef CONFIG_IDE_LED /* LED for ide not supported */
331#undef CONFIG_IDE_RESET /* reset for ide not supported */
332
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200333#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
334#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100335
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100337
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100339
340/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200341#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100342
343/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100345
346/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100348
349/*-----------------------------------------------------------------------
350 *
351 *-----------------------------------------------------------------------
352 *
353 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200354#define CONFIG_SYS_DER 0
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100355
356/*
357 * Init Memory Controller:
358 *
359 * BR0/1 and OR0/1 (FLASH)
360 */
361
362#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
363#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
364
365/* used to re-map FLASH both when starting from SRAM or FLASH:
366 * restrict access enough to keep SRAM working (if any)
367 * but not too much to meddle with FLASH accesses
368 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
370#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100371
372/*
373 * FLASH timing: Default value of OR0 after reset
374 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200375#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100376 OR_SCY_6_CLK | OR_TRLX)
377
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200378#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
379#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
380#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100381
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200382#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
383#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
384#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100385
386/*
387 * BR2/3 and OR2/3 (SDRAM)
388 *
389 */
390#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
391#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
392#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */
393
394/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200395#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100396
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200397#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
398#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100399
400#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200401#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
402#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100403#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200404#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
405#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
406#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
407#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100408 BR_PS_8 | BR_MS_UPMB | BR_V )
409#endif /* CONFIG_CAN_DRIVER */
410
411/*
412 * 4096 Rows from SDRAM example configuration
413 * 1000 factor s -> ms
414 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
415 * 4 Number of refresh cycles per period
416 * 64 Refresh cycle in ms per number of rows
417 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200418#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100419
420/*
421 * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
422 *
423 * CPUclock(MHz) * 31.2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200424 * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100425 * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16
426 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200427 * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us
428 * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us
429 * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us
430 * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100431 *
432 * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
433 * be met also in the default configuration, i.e. if environment variable
434 * 'cpuclk' is not set.
435 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200436#define CONFIG_SYS_MAMR_PTA 128
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100437
438/*
439 * Memory Periodic Timer Prescaler Register (MPTPR) values.
440 */
441/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200442#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100443/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200444#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100445
446/*
447 * MAMR settings for SDRAM
448 */
449
450/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200451#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100452 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
453 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
454/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200455#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100456 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
457 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
458/* 10 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200459#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100460 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \
461 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
462
463/*
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100464 * Network configuration
465 */
466#define CONFIG_FEC_ENET /* enable ethernet on FEC */
467#define CONFIG_ETHER_ON_FEC1 /* ... for FEC1 */
468#define CONFIG_ETHER_ON_FEC2 /* ... for FEC2 */
469
470#define CONFIG_LAST_STAGE_INIT 1 /* Have to configure PHYs for Linux */
471
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200472/* CONFIG_SYS_DISCOVER_PHY only works with FEC if only one interface is enabled */
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100473#if (!defined(CONFIG_ETHER_ON_FEC1) || !defined(CONFIG_ETHER_ON_FEC2))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200474#define CONFIG_SYS_DISCOVER_PHY
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100475#endif
476
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200477#ifndef CONFIG_SYS_DISCOVER_PHY
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100478/* PHY addresses - hard wired in hardware */
479#define CONFIG_FEC1_PHY 1
480#define CONFIG_FEC2_PHY 2
481#endif
482
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -0500483#define CONFIG_MII_INIT 1
484
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100485#define CONFIG_NET_RETRY_COUNT 3
Heiko Schocher48690d82010-07-20 17:45:02 +0200486#define CONFIG_ETHPRIME "FEC"
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100487
Heiko Schocher7026ead2010-02-09 15:50:27 +0100488/* pass open firmware flat tree */
489#define CONFIG_OF_LIBFDT 1
490#define CONFIG_OF_BOARD_SETUP 1
491#define CONFIG_HWCONFIG 1
492
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100493#endif /* __CONFIG_H */