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Wolfgang Denk6ccec442006-10-24 14:42:37 +02001/*
2 * Copyright (C) 2005-2006 Atmel Corporation
3 *
4 * Configuration settings for the ATSTK1002 CPU daughterboard
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Wolfgang Denk6ccec442006-10-24 14:42:37 +02007 */
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
Andreas Bießmann5d73bc72010-11-04 23:15:30 +000011#include <asm/arch/hardware.h>
Haavard Skinnemoena23e2772008-05-19 11:36:28 +020012
Andreas Bießmanne3e8d462011-04-18 04:12:36 +000013#define CONFIG_AVR32
14#define CONFIG_AT32AP
15#define CONFIG_AT32AP7000
16#define CONFIG_ATSTK1002
17#define CONFIG_ATSTK1000
Wolfgang Denk6ccec442006-10-24 14:42:37 +020018
Wolfgang Denk6ccec442006-10-24 14:42:37 +020019/*
20 * Timer clock frequency. We're using the CPU-internal COUNT register
21 * for this, so this is equivalent to the CPU core clock frequency
22 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020023#define CONFIG_SYS_HZ 1000
Wolfgang Denk6ccec442006-10-24 14:42:37 +020024
25/*
Eirik Aanonsena4f3aab2007-09-12 13:32:37 +020026 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
27 * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
28 * PLL frequency.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020029 * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
Wolfgang Denk6ccec442006-10-24 14:42:37 +020030 */
Andreas Bießmanne3e8d462011-04-18 04:12:36 +000031#define CONFIG_PLL
32#define CONFIG_SYS_POWER_MANAGER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020033#define CONFIG_SYS_OSC0_HZ 20000000
34#define CONFIG_SYS_PLL0_DIV 1
35#define CONFIG_SYS_PLL0_MUL 7
36#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
Eirik Aanonsena4f3aab2007-09-12 13:32:37 +020037/*
38 * Set the CPU running at:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020039 * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
Eirik Aanonsena4f3aab2007-09-12 13:32:37 +020040 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041#define CONFIG_SYS_CLKDIV_CPU 0
Eirik Aanonsena4f3aab2007-09-12 13:32:37 +020042/*
43 * Set the HSB running at:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020044 * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
Eirik Aanonsena4f3aab2007-09-12 13:32:37 +020045 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020046#define CONFIG_SYS_CLKDIV_HSB 1
Eirik Aanonsena4f3aab2007-09-12 13:32:37 +020047/*
48 * Set the PBA running at:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049 * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
Eirik Aanonsena4f3aab2007-09-12 13:32:37 +020050 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020051#define CONFIG_SYS_CLKDIV_PBA 2
Eirik Aanonsena4f3aab2007-09-12 13:32:37 +020052/*
53 * Set the PBB running at:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020054 * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
Eirik Aanonsena4f3aab2007-09-12 13:32:37 +020055 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056#define CONFIG_SYS_CLKDIV_PBB 1
Wolfgang Denk6ccec442006-10-24 14:42:37 +020057
Haavard Skinnemoen1f36f732010-08-12 13:52:54 +070058/* Reserve VM regions for SDRAM and NOR flash */
59#define CONFIG_SYS_NR_VM_REGIONS 2
60
Wolfgang Denk6ccec442006-10-24 14:42:37 +020061/*
62 * The PLLOPT register controls the PLL like this:
63 * icp = PLLOPT<2>
64 * ivco = PLLOPT<1:0>
65 *
66 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
67 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068#define CONFIG_SYS_PLL0_OPT 0x04
Wolfgang Denk6ccec442006-10-24 14:42:37 +020069
Andreas Bießmannf4278b72010-11-04 23:15:31 +000070#define CONFIG_USART_BASE ATMEL_BASE_USART1
71#define CONFIG_USART_ID 1
Wolfgang Denk6ccec442006-10-24 14:42:37 +020072
73/* User serviceable stuff */
Andreas Bießmanne3e8d462011-04-18 04:12:36 +000074#define CONFIG_DOS_PARTITION
Haavard Skinnemoen8e687512006-12-17 18:56:46 +010075
Andreas Bießmanne3e8d462011-04-18 04:12:36 +000076#define CONFIG_CMDLINE_TAG
77#define CONFIG_SETUP_MEMORY_TAGS
78#define CONFIG_INITRD_TAG
Wolfgang Denk6ccec442006-10-24 14:42:37 +020079
80#define CONFIG_STACKSIZE (2048)
81
82#define CONFIG_BAUDRATE 115200
83#define CONFIG_BOOTARGS \
Eirik Aanonsene80e5852007-09-18 08:47:20 +020084 "console=ttyS0 root=/dev/mmcblk0p1 fbmem=600k rootwait=1"
Haavard Skinnemoen1b804b22007-03-21 19:47:36 +010085
86#define CONFIG_BOOTCOMMAND \
87 "fsload; bootm $(fileaddr)"
88
89/*
90 * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
91 * data on the serial line may interrupt the boot sequence.
92 */
Hans-Christian Egtvedt696dd132007-08-30 15:03:05 +020093#define CONFIG_BOOTDELAY 1
Andreas Bießmanne3e8d462011-04-18 04:12:36 +000094#define CONFIG_AUTOBOOT
95#define CONFIG_AUTOBOOT_KEYED
Wolfgang Denkc37207d2008-07-16 16:38:59 +020096#define CONFIG_AUTOBOOT_PROMPT \
97 "Press SPACE to abort autoboot in %d seconds\n", bootdelay
Haavard Skinnemoen1b804b22007-03-21 19:47:36 +010098#define CONFIG_AUTOBOOT_DELAY_STR "d"
99#define CONFIG_AUTOBOOT_STOP_STR " "
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200100
Haavard Skinnemoen9a24f472006-12-17 17:14:30 +0100101/*
Haavard Skinnemoen8b6684a2007-10-24 15:48:37 +0200102 * After booting the board for the first time, new ethernet addresses
103 * should be generated and assigned to the environment variables
104 * "ethaddr" and "eth1addr". This is normally done during production.
Haavard Skinnemoen9a24f472006-12-17 17:14:30 +0100105 */
Andreas Bießmanne3e8d462011-04-18 04:12:36 +0000106#define CONFIG_OVERWRITE_ETHADDR_ONCE
Haavard Skinnemoen9a24f472006-12-17 17:14:30 +0100107
Jon Loeliger2fd90ce2007-07-09 21:48:26 -0500108/*
109 * BOOTP options
110 */
111#define CONFIG_BOOTP_SUBNETMASK
112#define CONFIG_BOOTP_GATEWAY
113
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200114
Jon Loeliger0b361c92007-07-04 22:31:42 -0500115/*
116 * Command line configuration.
117 */
118#include <config_cmd_default.h>
119
120#define CONFIG_CMD_ASKENV
121#define CONFIG_CMD_DHCP
122#define CONFIG_CMD_EXT2
123#define CONFIG_CMD_FAT
124#define CONFIG_CMD_JFFS2
125#define CONFIG_CMD_MMC
Jon Loeliger0b361c92007-07-04 22:31:42 -0500126
David Brownell55ac7a72008-02-22 12:54:39 -0800127#undef CONFIG_CMD_FPGA
Jon Loeliger0b361c92007-07-04 22:31:42 -0500128#undef CONFIG_CMD_SETGETDCR
Wolfgang Denk74de7ae2009-04-01 23:34:12 +0200129#undef CONFIG_CMD_SOURCE
Jon Loeliger0b361c92007-07-04 22:31:42 -0500130#undef CONFIG_CMD_XIMG
131
Andreas Bießmanne3e8d462011-04-18 04:12:36 +0000132#define CONFIG_ATMEL_USART
133#define CONFIG_MACB
134#define CONFIG_PORTMUX_PIO
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_NR_PIOS 5
Andreas Bießmanne3e8d462011-04-18 04:12:36 +0000136#define CONFIG_SYS_HSDRAMC
137#define CONFIG_MMC
Sven Schnelle72fa4672011-10-21 14:49:25 +0200138#define CONFIG_GENERIC_ATMEL_MCI
139#define CONFIG_GENERIC_MMC
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200140
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_DCACHE_LINESZ 32
142#define CONFIG_SYS_ICACHE_LINESZ 32
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200143
144#define CONFIG_NR_DRAM_BANKS 1
145
Andreas Bießmann22178652011-06-28 04:15:58 +0000146#define CONFIG_SYS_FLASH_CFI
147#define CONFIG_FLASH_CFI_DRIVER
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200148
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_FLASH_BASE 0x00000000
150#define CONFIG_SYS_FLASH_SIZE 0x800000
151#define CONFIG_SYS_MAX_FLASH_BANKS 1
152#define CONFIG_SYS_MAX_FLASH_SECT 135
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200153
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
Andreas Bießmann47293c12011-04-18 04:12:44 +0000155#define CONFIG_SYS_TEXT_BASE 0x00000000
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200156
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
158#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
159#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200160
Andreas Bießmanne3e8d462011-04-18 04:12:36 +0000161#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200162#define CONFIG_ENV_SIZE 65536
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200164
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200166
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_MALLOC_LEN (256*1024)
168#define CONFIG_SYS_DMA_ALLOC_LEN (16384)
Haavard Skinnemoen1f4f2122006-11-20 15:53:10 +0100169
Haavard Skinnemoen8269ab52007-11-22 17:01:24 +0100170/* Allow 4MB for the kernel run-time image */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
172#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200173
174/* Other configuration settings that shouldn't have to change all that often */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_PROMPT "U-Boot> "
176#define CONFIG_SYS_CBSIZE 256
177#define CONFIG_SYS_MAXARGS 16
178#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
Andreas Bießmanne3e8d462011-04-18 04:12:36 +0000179#define CONFIG_SYS_LONGHELP
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200180
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE
182#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000)
183#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
Wolfgang Denk6ccec442006-10-24 14:42:37 +0200184
185#endif /* __CONFIG_H */