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wdenk4d75a502003-03-25 16:50:56 +00001/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25
26#ifdef CONFIG_PCI
27
28#include <pci.h>
wdenk5d232d02003-05-22 22:52:13 +000029#include <mpc8260.h>
wdenk4d75a502003-03-25 16:50:56 +000030#include <asm/m8260_pci.h>
wdenk3c74e322004-02-22 23:46:08 +000031#include <asm/io.h>
wdenk4d75a502003-03-25 16:50:56 +000032/*
wdenk3c74e322004-02-22 23:46:08 +000033 * Local->PCI map (from CPU) controlled by
wdenk4d75a502003-03-25 16:50:56 +000034 * MPC826x master window
35 *
wdenk3c74e322004-02-22 23:46:08 +000036 * 0x80000000 - 0xBFFFFFFF CPU2PCI space PCIBR0
37 * 0xF4000000 - 0xF7FFFFFF CPU2PCI space PCIBR1
wdenk8bde7f72003-06-27 21:31:46 +000038 *
wdenk3c74e322004-02-22 23:46:08 +000039 * 0x80000000 - 0x9FFFFFFF 0x80000000 - 0x9FFFFFFF (Outbound ATU #1)
40 * PCI Mem with prefetch
wdenk5d232d02003-05-22 22:52:13 +000041 *
wdenk3c74e322004-02-22 23:46:08 +000042 * 0xA0000000 - 0xBFFFFFFF 0xA0000000 - 0xBFFFFFFF (Outbound ATU #2)
43 * PCI Mem w/o prefetch
wdenk5d232d02003-05-22 22:52:13 +000044 *
wdenk3c74e322004-02-22 23:46:08 +000045 * 0xF4000000 - 0xF7FFFFFF 0x00000000 - 0x03FFFFFF (Outbound ATU #3)
46 * 32-bit PCI IO
wdenk8bde7f72003-06-27 21:31:46 +000047 *
wdenk4d75a502003-03-25 16:50:56 +000048 * PCI->Local map (from PCI)
wdenk3c74e322004-02-22 23:46:08 +000049 * MPC826x slave window controlled by
wdenk4d75a502003-03-25 16:50:56 +000050 *
wdenk3c74e322004-02-22 23:46:08 +000051 * 0x00000000 - 0x1FFFFFFF 0x00000000 - 0x1FFFFFFF (Inbound ATU #1)
52 * MPC826x local memory
wdenk4d75a502003-03-25 16:50:56 +000053 */
54
wdenk8bde7f72003-06-27 21:31:46 +000055/*
56 * Slave window that allows PCI masters to access MPC826x local memory.
wdenk4d75a502003-03-25 16:50:56 +000057 * This window is set up using the first set of Inbound ATU registers
58 */
59
wdenk8bde7f72003-06-27 21:31:46 +000060#ifndef CFG_PCI_SLV_MEM_LOCAL
wdenk3c74e322004-02-22 23:46:08 +000061#define PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */
wdenk8bde7f72003-06-27 21:31:46 +000062#else
63#define PCI_SLV_MEM_LOCAL CFG_PCI_SLV_MEM_LOCAL
wdenk5d232d02003-05-22 22:52:13 +000064#endif
65
66#ifndef CFG_PCI_SLV_MEM_BUS
wdenk3c74e322004-02-22 23:46:08 +000067#define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
wdenk5d232d02003-05-22 22:52:13 +000068#else
69#define PCI_SLV_MEM_BUS CFG_PCI_SLV_MEM_BUS
70#endif
71
72#ifndef CFG_PICMR0_MASK_ATTRIB
wdenk4d75a502003-03-25 16:50:56 +000073#define PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
wdenk8bde7f72003-06-27 21:31:46 +000074 PICMR_PREFETCH_EN)
wdenk5d232d02003-05-22 22:52:13 +000075#else
76#define PICMR0_MASK_ATTRIB CFG_PICMR0_MASK_ATTRIB
77#endif
wdenk4d75a502003-03-25 16:50:56 +000078
wdenk8bde7f72003-06-27 21:31:46 +000079/*
wdenk5d232d02003-05-22 22:52:13 +000080 * These are the windows that allow the CPU to access PCI address space.
wdenk8bde7f72003-06-27 21:31:46 +000081 * All three PCI master windows, which allow the CPU to access PCI
82 * prefetch, non prefetch, and IO space (see below), must all fit within
wdenk5d232d02003-05-22 22:52:13 +000083 * these windows.
wdenk4d75a502003-03-25 16:50:56 +000084 */
85
wdenk5d232d02003-05-22 22:52:13 +000086/* PCIBR0 */
87#ifndef CFG_PCI_MSTR0_LOCAL
wdenk3c74e322004-02-22 23:46:08 +000088#define PCI_MSTR0_LOCAL 0x80000000 /* Local base */
wdenk8bde7f72003-06-27 21:31:46 +000089#else
wdenk5d232d02003-05-22 22:52:13 +000090#define PCI_MSTR0_LOCAL CFG_PCI_MSTR0_LOCAL
91#endif
92
93#ifndef CFG_PCIMSK0_MASK
wdenk3c74e322004-02-22 23:46:08 +000094#define PCIMSK0_MASK PCIMSK_1GB /* Size of window */
wdenk5d232d02003-05-22 22:52:13 +000095#else
96#define PCIMSK0_MASK CFG_PCIMSK0_MASK
97#endif
98
99/* PCIBR1 */
100#ifndef CFG_PCI_MSTR1_LOCAL
wdenk3c74e322004-02-22 23:46:08 +0000101#define PCI_MSTR1_LOCAL 0xF4000000 /* Local base */
wdenk8bde7f72003-06-27 21:31:46 +0000102#else
103#define PCI_MSTR1_LOCAL CFG_PCI_MSTR1_LOCAL
wdenk5d232d02003-05-22 22:52:13 +0000104#endif
105
106#ifndef CFG_PCIMSK1_MASK
wdenk3c74e322004-02-22 23:46:08 +0000107#define PCIMSK1_MASK PCIMSK_64MB /* Size of window */
wdenk5d232d02003-05-22 22:52:13 +0000108#else
wdenk3c74e322004-02-22 23:46:08 +0000109#define PCIMSK1_MASK CFG_PCIMSK1_MASK
wdenk5d232d02003-05-22 22:52:13 +0000110#endif
wdenk4d75a502003-03-25 16:50:56 +0000111
wdenk8bde7f72003-06-27 21:31:46 +0000112/*
wdenk4d75a502003-03-25 16:50:56 +0000113 * Master window that allows the CPU to access PCI Memory (prefetch).
114 * This window will be setup with the first set of Outbound ATU registers
115 * in the bridge.
116 */
117
wdenk5d232d02003-05-22 22:52:13 +0000118#ifndef CFG_PCI_MSTR_MEM_LOCAL
wdenk3c74e322004-02-22 23:46:08 +0000119#define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
wdenk5d232d02003-05-22 22:52:13 +0000120#else
121#define PCI_MSTR_MEM_LOCAL CFG_PCI_MSTR_MEM_LOCAL
122#endif
123
124#ifndef CFG_PCI_MSTR_MEM_BUS
wdenk3c74e322004-02-22 23:46:08 +0000125#define PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
wdenk5d232d02003-05-22 22:52:13 +0000126#else
127#define PCI_MSTR_MEM_BUS CFG_PCI_MSTR_MEM_BUS
128#endif
129
130#ifndef CFG_CPU_PCI_MEM_START
131#define CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
132#else
133#define CPU_PCI_MEM_START CFG_CPU_PCI_MEM_START
134#endif
135
136#ifndef CFG_PCI_MSTR_MEM_SIZE
wdenk3c74e322004-02-22 23:46:08 +0000137#define PCI_MSTR_MEM_SIZE 0x10000000 /* 256MB */
wdenk5d232d02003-05-22 22:52:13 +0000138#else
139#define PCI_MSTR_MEM_SIZE CFG_PCI_MSTR_MEM_SIZE
140#endif
141
142#ifndef CFG_POCMR0_MASK_ATTRIB
wdenk4d75a502003-03-25 16:50:56 +0000143#define POCMR0_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
wdenk5d232d02003-05-22 22:52:13 +0000144#else
145#define POCMR0_MASK_ATTRIB CFG_POCMR0_MASK_ATTRIB
146#endif
wdenk4d75a502003-03-25 16:50:56 +0000147
wdenk8bde7f72003-06-27 21:31:46 +0000148/*
wdenk4d75a502003-03-25 16:50:56 +0000149 * Master window that allows the CPU to access PCI Memory (non-prefetch).
150 * This window will be setup with the second set of Outbound ATU registers
151 * in the bridge.
152 */
153
wdenk8bde7f72003-06-27 21:31:46 +0000154#ifndef CFG_PCI_MSTR_MEMIO_LOCAL
wdenk3c74e322004-02-22 23:46:08 +0000155#define PCI_MSTR_MEMIO_LOCAL 0x90000000 /* Local base */
wdenk8bde7f72003-06-27 21:31:46 +0000156#else
157#define PCI_MSTR_MEMIO_LOCAL CFG_PCI_MSTR_MEMIO_LOCAL
wdenk5d232d02003-05-22 22:52:13 +0000158#endif
159
wdenk8bde7f72003-06-27 21:31:46 +0000160#ifndef CFG_PCI_MSTR_MEMIO_BUS
wdenk3c74e322004-02-22 23:46:08 +0000161#define PCI_MSTR_MEMIO_BUS 0x90000000 /* PCI base */
wdenk8bde7f72003-06-27 21:31:46 +0000162#else
163#define PCI_MSTR_MEMIO_BUS CFG_PCI_MSTR_MEMIO_BUS
wdenk5d232d02003-05-22 22:52:13 +0000164#endif
165
wdenk8bde7f72003-06-27 21:31:46 +0000166#ifndef CFG_CPU_PCI_MEMIO_START
167#define CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
168#else
169#define CPU_PCI_MEMIO_START CFG_CPU_PCI_MEMIO_START
wdenk5d232d02003-05-22 22:52:13 +0000170#endif
171
wdenk8bde7f72003-06-27 21:31:46 +0000172#ifndef CFG_PCI_MSTR_MEMIO_SIZE
wdenk3c74e322004-02-22 23:46:08 +0000173#define PCI_MSTR_MEMIO_SIZE 0x10000000 /* 256 MB */
wdenk8bde7f72003-06-27 21:31:46 +0000174#else
175#define PCI_MSTR_MEMIO_SIZE CFG_PCI_MSTR_MEMIO_SIZE
wdenk5d232d02003-05-22 22:52:13 +0000176#endif
177
178#ifndef CFG_POCMR1_MASK_ATTRIB
wdenk3c74e322004-02-22 23:46:08 +0000179#define POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE)
wdenk5d232d02003-05-22 22:52:13 +0000180#else
181#define POCMR1_MASK_ATTRIB CFG_POCMR1_MASK_ATTRIB
182#endif
wdenk4d75a502003-03-25 16:50:56 +0000183
wdenk8bde7f72003-06-27 21:31:46 +0000184/*
wdenk4d75a502003-03-25 16:50:56 +0000185 * Master window that allows the CPU to access PCI IO space.
186 * This window will be setup with the third set of Outbound ATU registers
187 * in the bridge.
188 */
189
wdenk8bde7f72003-06-27 21:31:46 +0000190#ifndef CFG_PCI_MSTR_IO_LOCAL
wdenk3c74e322004-02-22 23:46:08 +0000191#define PCI_MSTR_IO_LOCAL 0xA0000000 /* Local base */
wdenk8bde7f72003-06-27 21:31:46 +0000192#else
193#define PCI_MSTR_IO_LOCAL CFG_PCI_MSTR_IO_LOCAL
wdenk66fd3d12003-05-18 11:30:09 +0000194#endif
wdenk5d232d02003-05-22 22:52:13 +0000195
wdenk8bde7f72003-06-27 21:31:46 +0000196#ifndef CFG_PCI_MSTR_IO_BUS
wdenk3c74e322004-02-22 23:46:08 +0000197#define PCI_MSTR_IO_BUS 0xA0000000 /* PCI base */
wdenk8bde7f72003-06-27 21:31:46 +0000198#else
199#define PCI_MSTR_IO_BUS CFG_PCI_MSTR_IO_BUS
wdenk5d232d02003-05-22 22:52:13 +0000200#endif
201
wdenk8bde7f72003-06-27 21:31:46 +0000202#ifndef CFG_CPU_PCI_IO_START
203#define CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
204#else
205#define CPU_PCI_IO_START CFG_CPU_PCI_IO_START
wdenk5d232d02003-05-22 22:52:13 +0000206#endif
207
wdenk8bde7f72003-06-27 21:31:46 +0000208#ifndef CFG_PCI_MSTR_IO_SIZE
wdenk3c74e322004-02-22 23:46:08 +0000209#define PCI_MSTR_IO_SIZE 0x10000000 /* 256MB */
wdenk8bde7f72003-06-27 21:31:46 +0000210#else
211#define PCI_MSTR_IO_SIZE CFG_PCI_MSTR_IO_SIZE
wdenk5d232d02003-05-22 22:52:13 +0000212#endif
213
214#ifndef CFG_POCMR2_MASK_ATTRIB
wdenk3c74e322004-02-22 23:46:08 +0000215#define POCMR2_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PCI_IO)
wdenk5d232d02003-05-22 22:52:13 +0000216#else
217#define POCMR2_MASK_ATTRIB CFG_POCMR2_MASK_ATTRIB
218#endif
wdenk4d75a502003-03-25 16:50:56 +0000219
220/* PCI bus configuration registers.
221 */
222
223#define PCI_CLASS_BRIDGE_CTLR 0x06
224
225
wdenk3c74e322004-02-22 23:46:08 +0000226static inline void pci_outl (u32 addr, u32 data)
wdenk4d75a502003-03-25 16:50:56 +0000227{
wdenk3c74e322004-02-22 23:46:08 +0000228 *(volatile u32 *) addr = cpu_to_le32 (data);
wdenk4d75a502003-03-25 16:50:56 +0000229}
230
wdenk3c74e322004-02-22 23:46:08 +0000231void pci_mpc8250_init (struct pci_controller *hose)
wdenk4d75a502003-03-25 16:50:56 +0000232{
wdenk5d232d02003-05-22 22:52:13 +0000233#ifdef CONFIG_MPC8266ADS
wdenk3c74e322004-02-22 23:46:08 +0000234 DECLARE_GLOBAL_DATA_PTR;
wdenk5d232d02003-05-22 22:52:13 +0000235#endif
wdenk3c74e322004-02-22 23:46:08 +0000236 u16 tempShort;
wdenk4d75a502003-03-25 16:50:56 +0000237
wdenk3c74e322004-02-22 23:46:08 +0000238 volatile immap_t *immap = (immap_t *) CFG_IMMR;
239 pci_dev_t host_devno = PCI_BDF (0, 0, 0);
wdenk4d75a502003-03-25 16:50:56 +0000240
wdenk3c74e322004-02-22 23:46:08 +0000241 pci_setup_indirect (hose, CFG_IMMR + PCI_CFG_ADDR_REG,
242 CFG_IMMR + PCI_CFG_DATA_REG);
243
244 /*
245 * Setting required to enable local bus for PCI (SIUMCR [LBPC]).
246 */
wdenk5d232d02003-05-22 22:52:13 +0000247#ifdef CONFIG_MPC8266ADS
wdenk3c74e322004-02-22 23:46:08 +0000248 immap->im_siu_conf.sc_siumcr =
249 (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
250 | SIUMCR_LBPC01;
wdenk5d232d02003-05-22 22:52:13 +0000251#else
wdenk3c74e322004-02-22 23:46:08 +0000252 /*
253 * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
254 * and local bus for PCI (SIUMCR [LBPC]).
255 */
256 immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
257 ~SIUMCR_LBPC11 &
wdenk8bde7f72003-06-27 21:31:46 +0000258 ~SIUMCR_CS10PC11 &
wdenk3c74e322004-02-22 23:46:08 +0000259 ~SIUMCR_LBPC11) |
260 SIUMCR_LBPC01 |
261 SIUMCR_CS10PC01 |
262 SIUMCR_APPC10;
wdenk5d232d02003-05-22 22:52:13 +0000263#endif
wdenk4d75a502003-03-25 16:50:56 +0000264
wdenk3c74e322004-02-22 23:46:08 +0000265 /* Make PCI lowest priority */
266 /* Each 4 bits is a device bus request and the MS 4bits
267 is highest priority */
268 /* Bus 4bit value
269 --- ----------
270 CPM high 0b0000
271 CPM middle 0b0001
272 CPM low 0b0010
273 PCI reguest 0b0011
274 Reserved 0b0100
275 Reserved 0b0101
276 Internal Core 0b0110
277 External Master 1 0b0111
278 External Master 2 0b1000
279 External Master 3 0b1001
280 The rest are reserved */
281 immap->im_siu_conf.sc_ppc_alrh = 0x61207893;
wdenk4d75a502003-03-25 16:50:56 +0000282
wdenk3c74e322004-02-22 23:46:08 +0000283 /* Park bus on core while modifying PCI Bus accesses */
284 immap->im_siu_conf.sc_ppc_acr = 0x6;
wdenk4d75a502003-03-25 16:50:56 +0000285
wdenk3c74e322004-02-22 23:46:08 +0000286 /*
287 * Set up master windows that allow the CPU to access PCI space. These
288 * windows are set up using the two SIU PCIBR registers.
289 */
290 immap->im_memctl.memc_pcimsk0 = PCIMSK0_MASK;
291 immap->im_memctl.memc_pcibr0 = PCI_MSTR0_LOCAL | PCIBR_ENABLE;
wdenk5d232d02003-05-22 22:52:13 +0000292
293#ifdef CONFIG_MPC8266ADS
wdenkd4326ac2004-04-18 21:17:30 +0000294 immap->im_memctl.memc_pcimsk1 = PCIMSK1_MASK;
295 immap->im_memctl.memc_pcibr1 = PCI_MSTR1_LOCAL | PCIBR_ENABLE;
wdenk8bde7f72003-06-27 21:31:46 +0000296#endif
wdenk4d75a502003-03-25 16:50:56 +0000297
wdenk3c74e322004-02-22 23:46:08 +0000298 /* Release PCI RST (by default the PCI RST signal is held low) */
299 immap->im_pci.pci_gcr = cpu_to_le32 (PCIGCR_PCI_BUS_EN);
wdenk4d75a502003-03-25 16:50:56 +0000300
wdenk3c74e322004-02-22 23:46:08 +0000301 /* give it some time */
302 {
wdenk8bde7f72003-06-27 21:31:46 +0000303#ifdef CONFIG_MPC8266ADS
304 /* Give the PCI cards more time to initialize before query
wdenk3c74e322004-02-22 23:46:08 +0000305 This might be good for other boards also
306 */
307 int i;
308
309 for (i = 0; i < 1000; ++i)
wdenk5d232d02003-05-22 22:52:13 +0000310#endif
wdenk3c74e322004-02-22 23:46:08 +0000311 udelay (1000);
312 }
wdenk4d75a502003-03-25 16:50:56 +0000313
wdenk3c74e322004-02-22 23:46:08 +0000314 /*
315 * Set up master window that allows the CPU to access PCI Memory (prefetch)
316 * space. This window is set up using the first set of Outbound ATU registers.
317 */
318 immap->im_pci.pci_potar0 = cpu_to_le32 (PCI_MSTR_MEM_BUS >> 12); /* PCI base */
319 immap->im_pci.pci_pobar0 = cpu_to_le32 (PCI_MSTR_MEM_LOCAL >> 12); /* Local base */
320 immap->im_pci.pci_pocmr0 = cpu_to_le32 (POCMR0_MASK_ATTRIB); /* Size & attribute */
wdenk4d75a502003-03-25 16:50:56 +0000321
wdenk3c74e322004-02-22 23:46:08 +0000322 /*
323 * Set up master window that allows the CPU to access PCI Memory (non-prefetch)
324 * space. This window is set up using the second set of Outbound ATU registers.
325 */
326 immap->im_pci.pci_potar1 = cpu_to_le32 (PCI_MSTR_MEMIO_BUS >> 12); /* PCI base */
327 immap->im_pci.pci_pobar1 = cpu_to_le32 (PCI_MSTR_MEMIO_LOCAL >> 12); /* Local base */
328 immap->im_pci.pci_pocmr1 = cpu_to_le32 (POCMR1_MASK_ATTRIB); /* Size & attribute */
wdenk8bde7f72003-06-27 21:31:46 +0000329
wdenk3c74e322004-02-22 23:46:08 +0000330 /*
331 * Set up master window that allows the CPU to access PCI IO space. This window
332 * is set up using the third set of Outbound ATU registers.
333 */
334 immap->im_pci.pci_potar2 = cpu_to_le32 (PCI_MSTR_IO_BUS >> 12); /* PCI base */
335 immap->im_pci.pci_pobar2 = cpu_to_le32 (PCI_MSTR_IO_LOCAL >> 12); /* Local base */
336 immap->im_pci.pci_pocmr2 = cpu_to_le32 (POCMR2_MASK_ATTRIB); /* Size & attribute */
wdenk4d75a502003-03-25 16:50:56 +0000337
wdenk3c74e322004-02-22 23:46:08 +0000338 /*
339 * Set up slave window that allows PCI masters to access MPC826x local memory.
340 * This window is set up using the first set of Inbound ATU registers
341 */
342 immap->im_pci.pci_pitar0 = cpu_to_le32 (PCI_SLV_MEM_LOCAL >> 12); /* PCI base */
343 immap->im_pci.pci_pibar0 = cpu_to_le32 (PCI_SLV_MEM_BUS >> 12); /* Local base */
344 immap->im_pci.pci_picmr0 = cpu_to_le32 (PICMR0_MASK_ATTRIB); /* Size & attribute */
wdenk4d75a502003-03-25 16:50:56 +0000345
wdenk3c74e322004-02-22 23:46:08 +0000346 /* See above for description - puts PCI request as highest priority */
347 immap->im_siu_conf.sc_ppc_alrh = 0x03124567;
wdenk4d75a502003-03-25 16:50:56 +0000348
wdenk3c74e322004-02-22 23:46:08 +0000349 /* Park the bus on the PCI */
350 immap->im_siu_conf.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
wdenk4d75a502003-03-25 16:50:56 +0000351
wdenk3c74e322004-02-22 23:46:08 +0000352 /* Host mode - specify the bridge as a host-PCI bridge */
wdenk4d75a502003-03-25 16:50:56 +0000353
wdenk3c74e322004-02-22 23:46:08 +0000354 pci_hose_write_config_byte (hose, host_devno, PCI_CLASS_CODE,
355 PCI_CLASS_BRIDGE_CTLR);
wdenk4d75a502003-03-25 16:50:56 +0000356
wdenk3c74e322004-02-22 23:46:08 +0000357 /* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */
358 pci_hose_read_config_word (hose, host_devno, PCI_COMMAND, &tempShort);
359 pci_hose_write_config_word (hose, host_devno, PCI_COMMAND,
360 tempShort | PCI_COMMAND_MASTER |
361 PCI_COMMAND_MEMORY);
wdenk4d75a502003-03-25 16:50:56 +0000362
wdenk7a8e9bed2003-05-31 18:35:21 +0000363 /* do some bridge init, should be done on all 8260 based bridges */
wdenk3c74e322004-02-22 23:46:08 +0000364 pci_hose_write_config_byte (hose, host_devno, PCI_CACHE_LINE_SIZE,
365 0x08);
366 pci_hose_write_config_byte (hose, host_devno, PCI_LATENCY_TIMER,
367 0xF8);
wdenk7a8e9bed2003-05-31 18:35:21 +0000368
wdenk3c74e322004-02-22 23:46:08 +0000369 hose->first_busno = 0;
370 hose->last_busno = 0xff;
wdenk4d75a502003-03-25 16:50:56 +0000371
wdenk3c74e322004-02-22 23:46:08 +0000372 /* System memory space */
wdenk5d232d02003-05-22 22:52:13 +0000373#ifdef CONFIG_MPC8266ADS
wdenk3c74e322004-02-22 23:46:08 +0000374 pci_set_region (hose->regions + 0,
375 PCI_SLV_MEM_BUS,
376 PCI_SLV_MEM_LOCAL,
377 gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY);
wdenk5d232d02003-05-22 22:52:13 +0000378#else
wdenk3c74e322004-02-22 23:46:08 +0000379 pci_set_region (hose->regions + 0,
380 CFG_SDRAM_BASE,
381 CFG_SDRAM_BASE,
382 0x4000000, PCI_REGION_MEM | PCI_REGION_MEMORY);
wdenk5d232d02003-05-22 22:52:13 +0000383#endif
wdenk4d75a502003-03-25 16:50:56 +0000384
wdenk3c74e322004-02-22 23:46:08 +0000385 /* PCI memory space */
wdenk5d232d02003-05-22 22:52:13 +0000386#ifdef CONFIG_MPC8266ADS
wdenk3c74e322004-02-22 23:46:08 +0000387 pci_set_region (hose->regions + 1,
388 PCI_MSTR_MEMIO_BUS,
389 PCI_MSTR_MEMIO_LOCAL,
390 PCI_MSTR_MEMIO_SIZE, PCI_REGION_MEM);
wdenk5d232d02003-05-22 22:52:13 +0000391#else
wdenk3c74e322004-02-22 23:46:08 +0000392 pci_set_region (hose->regions + 1,
393 PCI_MSTR_MEM_BUS,
394 PCI_MSTR_MEM_LOCAL,
395 PCI_MSTR_MEM_SIZE, PCI_REGION_MEM);
wdenk5d232d02003-05-22 22:52:13 +0000396#endif
wdenk4d75a502003-03-25 16:50:56 +0000397
wdenk3c74e322004-02-22 23:46:08 +0000398 /* PCI I/O space */
399 pci_set_region (hose->regions + 2,
400 PCI_MSTR_IO_BUS,
401 PCI_MSTR_IO_LOCAL, PCI_MSTR_IO_SIZE, PCI_REGION_IO);
wdenk4d75a502003-03-25 16:50:56 +0000402
wdenk3c74e322004-02-22 23:46:08 +0000403 hose->region_count = 3;
wdenk4d75a502003-03-25 16:50:56 +0000404
wdenk3c74e322004-02-22 23:46:08 +0000405 pci_register_hose (hose);
406 /* Mask off master abort machine checks */
407 immap->im_pci.pci_emr &= cpu_to_le32 (~PCI_ERROR_PCI_NO_RSP);
408 eieio ();
wdenk4d75a502003-03-25 16:50:56 +0000409
wdenk3c74e322004-02-22 23:46:08 +0000410 hose->last_busno = pci_hose_scan (hose);
411
412
413 /* clear the error in the error status register */
414 immap->im_pci.pci_esr = cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);
415
416 /* unmask master abort machine checks */
417 immap->im_pci.pci_emr |= cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);
wdenk4d75a502003-03-25 16:50:56 +0000418}
419
wdenk3c74e322004-02-22 23:46:08 +0000420#endif /* CONFIG_PCI */