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wdenkc6097192002-11-03 00:24:07 +00001/*
wdenkd4ca31c2004-01-02 14:00:00 +00002 * (C) Copyright 2000-2004
wdenkc6097192002-11-03 00:24:07 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
wdenkd4ca31c2004-01-02 14:00:00 +000024#if 0
25#define DEBUG
26#endif
wdenk73a8b272003-06-05 19:27:42 +000027
wdenkc6097192002-11-03 00:24:07 +000028#include <common.h>
29#include <mpc8xx.h>
wdenk71f95112003-06-15 22:40:42 +000030#include <environment.h>
wdenkc6097192002-11-03 00:24:07 +000031
wdenke9132ea2004-04-24 23:23:30 +000032#include <asm/processor.h>
33
34#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M)
35# ifndef CFG_OR_TIMING_FLASH_AT_50MHZ
36# define CFG_OR_TIMING_FLASH_AT_50MHZ (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
37 OR_SCY_2_CLK | OR_EHTR | OR_BI)
38# endif
39#endif /* CONFIG_TQM8xxL/M, !TQM866M */
40
wdenkc6097192002-11-03 00:24:07 +000041#ifndef CFG_ENV_ADDR
42#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
43#endif
44
45flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
46
47/*-----------------------------------------------------------------------
48 * Functions
49 */
50static ulong flash_get_size (vu_long *addr, flash_info_t *info);
51static int write_word (flash_info_t *info, ulong dest, ulong data);
52
53/*-----------------------------------------------------------------------
54 */
55
56unsigned long flash_init (void)
57{
58 volatile immap_t *immap = (immap_t *)CFG_IMMR;
59 volatile memctl8xx_t *memctl = &immap->im_memctl;
60 unsigned long size_b0, size_b1;
61 int i;
62
wdenke9132ea2004-04-24 23:23:30 +000063#ifdef CFG_OR_TIMING_FLASH_AT_50MHZ
64 int scy, trlx, flash_or_timing, clk_diff;
65
66 DECLARE_GLOBAL_DATA_PTR;
67
68 scy = (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4;
69 if (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) {
70 trlx = OR_TRLX;
71 scy *= 2;
72 } else
73 trlx = 0;
74
75 /* We assume that each 10MHz of bus clock require 1-clk SCY
76 * adjustment.
77 */
78 clk_diff = (gd->bus_clk / 1000000) - 50;
79
80 /* We need proper rounding here. This is what the "+5" and "-5"
81 * are here for.
82 */
83 if (clk_diff >= 0)
84 scy += (clk_diff + 5) / 10;
85 else
86 scy += (clk_diff - 5) / 10;
87
88 /* For bus frequencies above 50MHz, we want to use relaxed timing
89 * (OR_TRLX).
90 */
91 if (gd->bus_clk >= 50000000)
92 trlx = OR_TRLX;
93 else
94 trlx = 0;
95
96 if (trlx)
97 scy /= 2;
98
99 if (scy > 0xf)
100 scy = 0xf;
101 if (scy < 1)
102 scy = 1;
103
104 flash_or_timing = (scy << 4) | trlx |
105 (CFG_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK));
106#endif
wdenkc6097192002-11-03 00:24:07 +0000107 /* Init: no FLASHes known */
108 for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
109 flash_info[i].flash_id = FLASH_UNKNOWN;
110 }
111
112 /* Static FLASH Bank configuration here - FIXME XXX */
113
wdenk73a8b272003-06-05 19:27:42 +0000114 debug ("\n## Get flash bank 1 size @ 0x%08x\n",FLASH_BASE0_PRELIM);
115
wdenkc6097192002-11-03 00:24:07 +0000116 size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
117
wdenk73a8b272003-06-05 19:27:42 +0000118 debug ("## Get flash bank 2 size @ 0x%08x\n",FLASH_BASE1_PRELIM);
119
wdenkc6097192002-11-03 00:24:07 +0000120 if (flash_info[0].flash_id == FLASH_UNKNOWN) {
121 printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
122 size_b0, size_b0<<20);
123 }
124
125 size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
126
wdenk73a8b272003-06-05 19:27:42 +0000127 debug ("## Prelim. Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
128
wdenkc6097192002-11-03 00:24:07 +0000129 if (size_b1 > size_b0) {
130 printf ("## ERROR: "
131 "Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
132 size_b1, size_b1<<20,
133 size_b0, size_b0<<20
134 );
135 flash_info[0].flash_id = FLASH_UNKNOWN;
136 flash_info[1].flash_id = FLASH_UNKNOWN;
137 flash_info[0].sector_count = -1;
138 flash_info[1].sector_count = -1;
139 flash_info[0].size = 0;
140 flash_info[1].size = 0;
141 return (0);
142 }
143
wdenk73a8b272003-06-05 19:27:42 +0000144 debug ("## Before remap: "
145 "BR0: 0x%08x OR0: 0x%08x "
146 "BR1: 0x%08x OR1: 0x%08x\n",
147 memctl->memc_br0, memctl->memc_or0,
148 memctl->memc_br1, memctl->memc_or1);
149
wdenkc6097192002-11-03 00:24:07 +0000150 /* Remap FLASH according to real size */
wdenke9132ea2004-04-24 23:23:30 +0000151#ifndef CFG_OR_TIMING_FLASH_AT_50MHZ
wdenkc6097192002-11-03 00:24:07 +0000152 memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
wdenke9132ea2004-04-24 23:23:30 +0000153#else
154 memctl->memc_or0 = flash_or_timing | (-size_b0 & OR_AM_MSK);
155#endif
wdenkc6097192002-11-03 00:24:07 +0000156 memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
157
wdenk73a8b272003-06-05 19:27:42 +0000158 debug ("## BR0: 0x%08x OR0: 0x%08x\n",
159 memctl->memc_br0, memctl->memc_or0);
160
wdenkc6097192002-11-03 00:24:07 +0000161 /* Re-do sizing to get full correct info */
162 size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
163
164#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
165 /* monitor protection ON by default */
wdenk71f95112003-06-15 22:40:42 +0000166 debug ("Protect monitor: %08lx ... %08lx\n",
167 (ulong)CFG_MONITOR_BASE,
168 (ulong)CFG_MONITOR_BASE + monitor_flash_len - 1);
169
wdenkc6097192002-11-03 00:24:07 +0000170 flash_protect(FLAG_PROTECT_SET,
171 CFG_MONITOR_BASE,
wdenk71f95112003-06-15 22:40:42 +0000172 CFG_MONITOR_BASE + monitor_flash_len - 1,
wdenkc6097192002-11-03 00:24:07 +0000173 &flash_info[0]);
174#endif
175
176#ifdef CFG_ENV_IS_IN_FLASH
177 /* ENV protection ON by default */
wdenk71f95112003-06-15 22:40:42 +0000178# ifdef CFG_ENV_ADDR_REDUND
wdenke0ac62d2003-08-17 18:55:18 +0000179 debug ("Protect primary environment: %08lx ... %08lx\n",
wdenk71f95112003-06-15 22:40:42 +0000180 (ulong)CFG_ENV_ADDR,
181 (ulong)CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1);
wdenke0ac62d2003-08-17 18:55:18 +0000182# else
183 debug ("Protect environment: %08lx ... %08lx\n",
184 (ulong)CFG_ENV_ADDR,
185 (ulong)CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1);
186# endif
wdenk71f95112003-06-15 22:40:42 +0000187
wdenkc6097192002-11-03 00:24:07 +0000188 flash_protect(FLAG_PROTECT_SET,
189 CFG_ENV_ADDR,
wdenk71f95112003-06-15 22:40:42 +0000190 CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
191 &flash_info[0]);
192#endif
193
194#ifdef CFG_ENV_ADDR_REDUND
195 debug ("Protect redundand environment: %08lx ... %08lx\n",
196 (ulong)CFG_ENV_ADDR_REDUND,
197 (ulong)CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1);
198
199 flash_protect(FLAG_PROTECT_SET,
200 CFG_ENV_ADDR_REDUND,
201 CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
wdenkc6097192002-11-03 00:24:07 +0000202 &flash_info[0]);
203#endif
204
205 if (size_b1) {
wdenke9132ea2004-04-24 23:23:30 +0000206#ifndef CFG_OR_TIMING_FLASH_AT_50MHZ
wdenkc6097192002-11-03 00:24:07 +0000207 memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
wdenke9132ea2004-04-24 23:23:30 +0000208#else
209 memctl->memc_or1 = flash_or_timing | (-size_b1 & 0xFFFF8000);
210#endif
wdenkc6097192002-11-03 00:24:07 +0000211 memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) |
212 BR_MS_GPCM | BR_V;
213
wdenk73a8b272003-06-05 19:27:42 +0000214 debug ("## BR1: 0x%08x OR1: 0x%08x\n",
215 memctl->memc_br1, memctl->memc_or1);
216
wdenkc6097192002-11-03 00:24:07 +0000217 /* Re-do sizing to get full correct info */
218 size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0),
219 &flash_info[1]);
220
221#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
222 /* monitor protection ON by default */
223 flash_protect(FLAG_PROTECT_SET,
224 CFG_MONITOR_BASE,
wdenk3b57fe02003-05-30 12:48:29 +0000225 CFG_MONITOR_BASE+monitor_flash_len-1,
wdenkc6097192002-11-03 00:24:07 +0000226 &flash_info[1]);
227#endif
228
229#ifdef CFG_ENV_IS_IN_FLASH
230 /* ENV protection ON by default */
231 flash_protect(FLAG_PROTECT_SET,
232 CFG_ENV_ADDR,
233 CFG_ENV_ADDR+CFG_ENV_SIZE-1,
234 &flash_info[1]);
235#endif
236 } else {
237 memctl->memc_br1 = 0; /* invalidate bank */
238
239 flash_info[1].flash_id = FLASH_UNKNOWN;
240 flash_info[1].sector_count = -1;
wdenk73a8b272003-06-05 19:27:42 +0000241 flash_info[1].size = 0;
242
243 debug ("## DISABLE BR1: 0x%08x OR1: 0x%08x\n",
244 memctl->memc_br1, memctl->memc_or1);
wdenkc6097192002-11-03 00:24:07 +0000245 }
246
wdenk73a8b272003-06-05 19:27:42 +0000247 debug ("## Final Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
248
wdenkc6097192002-11-03 00:24:07 +0000249 flash_info[0].size = size_b0;
250 flash_info[1].size = size_b1;
251
252 return (size_b0 + size_b1);
253}
254
255/*-----------------------------------------------------------------------
256 */
257void flash_print_info (flash_info_t *info)
258{
259 int i;
260
261 if (info->flash_id == FLASH_UNKNOWN) {
262 printf ("missing or unknown FLASH type\n");
263 return;
264 }
265
266 switch (info->flash_id & FLASH_VENDMASK) {
267 case FLASH_MAN_AMD: printf ("AMD "); break;
268 case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
269 default: printf ("Unknown Vendor "); break;
270 }
271
272 switch (info->flash_id & FLASH_TYPEMASK) {
wdenk71f95112003-06-15 22:40:42 +0000273#ifdef CONFIG_TQM8xxM /* mirror bit flash */
274 case FLASH_AMLV128U: printf ("AM29LV128ML (128Mbit, uniform sector size)\n");
275 break;
wdenkf12e5682003-07-07 20:07:54 +0000276 case FLASH_AMLV320U: printf ("AM29LV320ML (32Mbit, uniform sector size)\n");
277 break;
278 case FLASH_AMLV640U: printf ("AM29LV640ML (64Mbit, uniform sector size)\n");
279 break;
wdenkd4ca31c2004-01-02 14:00:00 +0000280 case FLASH_AMLV320B: printf ("AM29LV320MB (32Mbit, bottom boot sect)\n");
281 break;
wdenk71f95112003-06-15 22:40:42 +0000282# else /* ! TQM8xxM */
wdenkc6097192002-11-03 00:24:07 +0000283 case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
284 break;
285 case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
286 break;
287 case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
288 break;
289 case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
290 break;
wdenkc6097192002-11-03 00:24:07 +0000291 case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
292 break;
293 case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
294 break;
wdenk71f95112003-06-15 22:40:42 +0000295#endif /* TQM8xxM */
wdenkf12e5682003-07-07 20:07:54 +0000296 case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
297 break;
298 case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
299 break;
wdenkd4ca31c2004-01-02 14:00:00 +0000300 case FLASH_AMDL163B: printf ("AM29DL163B (16 Mbit, bottom boot sect)\n");
301 break;
wdenkc6097192002-11-03 00:24:07 +0000302 default: printf ("Unknown Chip Type\n");
303 break;
304 }
305
306 printf (" Size: %ld MB in %d Sectors\n",
307 info->size >> 20, info->sector_count);
308
309 printf (" Sector Start Addresses:");
310 for (i=0; i<info->sector_count; ++i) {
311 if ((i % 5) == 0)
312 printf ("\n ");
313 printf (" %08lX%s",
314 info->start[i],
315 info->protect[i] ? " (RO)" : " "
316 );
317 }
318 printf ("\n");
319 return;
320}
321
322/*-----------------------------------------------------------------------
323 */
324
325
326/*-----------------------------------------------------------------------
327 */
328
329/*
330 * The following code cannot be run from FLASH!
331 */
332
333static ulong flash_get_size (vu_long *addr, flash_info_t *info)
334{
335 short i;
336 ulong value;
337 ulong base = (ulong)addr;
338
339 /* Write auto select command: read Manufacturer ID */
340 addr[0x0555] = 0x00AA00AA;
341 addr[0x02AA] = 0x00550055;
342 addr[0x0555] = 0x00900090;
343
344 value = addr[0];
345
wdenk73a8b272003-06-05 19:27:42 +0000346 debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value);
347
wdenkc6097192002-11-03 00:24:07 +0000348 switch (value) {
349 case AMD_MANUFACT:
wdenkd4ca31c2004-01-02 14:00:00 +0000350 debug ("Manufacturer: AMD\n");
wdenkc6097192002-11-03 00:24:07 +0000351 info->flash_id = FLASH_MAN_AMD;
352 break;
353 case FUJ_MANUFACT:
wdenkd4ca31c2004-01-02 14:00:00 +0000354 debug ("Manufacturer: FUJITSU\n");
wdenkc6097192002-11-03 00:24:07 +0000355 info->flash_id = FLASH_MAN_FUJ;
356 break;
357 default:
wdenkd4ca31c2004-01-02 14:00:00 +0000358 debug ("Manufacturer: *** unknown ***\n");
wdenkc6097192002-11-03 00:24:07 +0000359 info->flash_id = FLASH_UNKNOWN;
360 info->sector_count = 0;
361 info->size = 0;
362 return (0); /* no or unknown flash */
363 }
364
365 value = addr[1]; /* device ID */
366
wdenk73a8b272003-06-05 19:27:42 +0000367 debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value);
368
wdenkc6097192002-11-03 00:24:07 +0000369 switch (value) {
wdenk71f95112003-06-15 22:40:42 +0000370#ifdef CONFIG_TQM8xxM /* mirror bit flash */
371 case AMD_ID_MIRROR:
wdenkd4ca31c2004-01-02 14:00:00 +0000372 debug ("Mirror Bit flash: addr[14] = %08lX addr[15] = %08lX\n",
373 addr[14], addr[15]);
wdenkf12e5682003-07-07 20:07:54 +0000374 /* Special case for AMLV320MH/L */
375 if ((addr[14] & 0x00ff00ff) == 0x001d001d &&
wdenkd4ca31c2004-01-02 14:00:00 +0000376 (addr[15] & 0x00ff00ff) == 0x00000000) {
377 debug ("Chip: AMLV320MH/L\n");
wdenkf12e5682003-07-07 20:07:54 +0000378 info->flash_id += FLASH_AMLV320U;
379 info->sector_count = 64;
wdenkd4ca31c2004-01-02 14:00:00 +0000380 info->size = 0x00800000; /* => 8 MB */
wdenkf12e5682003-07-07 20:07:54 +0000381 break;
wdenk945af8d2003-07-16 21:53:01 +0000382 }
wdenk71f95112003-06-15 22:40:42 +0000383 switch(addr[14]) {
384 case AMD_ID_LV128U_2:
385 if (addr[15] != AMD_ID_LV128U_3) {
wdenkd4ca31c2004-01-02 14:00:00 +0000386 debug ("Chip: AMLV128U -> unknown\n");
wdenk71f95112003-06-15 22:40:42 +0000387 info->flash_id = FLASH_UNKNOWN;
wdenkd4ca31c2004-01-02 14:00:00 +0000388 } else {
389 debug ("Chip: AMLV128U\n");
wdenk71f95112003-06-15 22:40:42 +0000390 info->flash_id += FLASH_AMLV128U;
391 info->sector_count = 256;
392 info->size = 0x02000000;
393 }
wdenkd4ca31c2004-01-02 14:00:00 +0000394 break; /* => 32 MB */
wdenkf12e5682003-07-07 20:07:54 +0000395 case AMD_ID_LV640U_2:
396 if (addr[15] != AMD_ID_LV640U_3) {
wdenkd4ca31c2004-01-02 14:00:00 +0000397 debug ("Chip: AMLV640U -> unknown\n");
wdenkf12e5682003-07-07 20:07:54 +0000398 info->flash_id = FLASH_UNKNOWN;
wdenkd4ca31c2004-01-02 14:00:00 +0000399 } else {
400 debug ("Chip: AMLV640U\n");
wdenkf12e5682003-07-07 20:07:54 +0000401 info->flash_id += FLASH_AMLV640U;
402 info->sector_count = 128;
403 info->size = 0x01000000;
404 }
wdenkd4ca31c2004-01-02 14:00:00 +0000405 break; /* => 16 MB */
406 case AMD_ID_LV320B_2:
407 if (addr[15] != AMD_ID_LV320B_3) {
408 debug ("Chip: AMLV320B -> unknown\n");
409 info->flash_id = FLASH_UNKNOWN;
410 } else {
411 debug ("Chip: AMLV320B\n");
412 info->flash_id += FLASH_AMLV320B;
413 info->sector_count = 71;
414 info->size = 0x00800000;
415 }
416 break; /* => 8 MB */
wdenk71f95112003-06-15 22:40:42 +0000417 default:
wdenkd4ca31c2004-01-02 14:00:00 +0000418 debug ("Chip: *** unknown ***\n");
wdenk71f95112003-06-15 22:40:42 +0000419 info->flash_id = FLASH_UNKNOWN;
420 break;
421 }
422 break;
423# else /* ! TQM8xxM */
wdenkc6097192002-11-03 00:24:07 +0000424 case AMD_ID_LV400T:
425 info->flash_id += FLASH_AM400T;
426 info->sector_count = 11;
427 info->size = 0x00100000;
wdenkd4ca31c2004-01-02 14:00:00 +0000428 break; /* => 1 MB */
wdenkc6097192002-11-03 00:24:07 +0000429
430 case AMD_ID_LV400B:
431 info->flash_id += FLASH_AM400B;
432 info->sector_count = 11;
433 info->size = 0x00100000;
wdenkd4ca31c2004-01-02 14:00:00 +0000434 break; /* => 1 MB */
wdenkc6097192002-11-03 00:24:07 +0000435
436 case AMD_ID_LV800T:
437 info->flash_id += FLASH_AM800T;
438 info->sector_count = 19;
439 info->size = 0x00200000;
wdenkd4ca31c2004-01-02 14:00:00 +0000440 break; /* => 2 MB */
wdenkc6097192002-11-03 00:24:07 +0000441
442 case AMD_ID_LV800B:
443 info->flash_id += FLASH_AM800B;
444 info->sector_count = 19;
445 info->size = 0x00200000;
wdenkd4ca31c2004-01-02 14:00:00 +0000446 break; /* => 2 MB */
wdenkc6097192002-11-03 00:24:07 +0000447
wdenkc6097192002-11-03 00:24:07 +0000448 case AMD_ID_LV320T:
449 info->flash_id += FLASH_AM320T;
450 info->sector_count = 71;
451 info->size = 0x00800000;
wdenkd4ca31c2004-01-02 14:00:00 +0000452 break; /* => 8 MB */
wdenkc6097192002-11-03 00:24:07 +0000453
454 case AMD_ID_LV320B:
455 info->flash_id += FLASH_AM320B;
456 info->sector_count = 71;
457 info->size = 0x00800000;
wdenkd4ca31c2004-01-02 14:00:00 +0000458 break; /* => 8 MB */
wdenk71f95112003-06-15 22:40:42 +0000459#endif /* TQM8xxM */
wdenkf12e5682003-07-07 20:07:54 +0000460
461 case AMD_ID_LV160T:
462 info->flash_id += FLASH_AM160T;
463 info->sector_count = 35;
464 info->size = 0x00400000;
wdenkd4ca31c2004-01-02 14:00:00 +0000465 break; /* => 4 MB */
wdenkf12e5682003-07-07 20:07:54 +0000466
467 case AMD_ID_LV160B:
468 info->flash_id += FLASH_AM160B;
469 info->sector_count = 35;
470 info->size = 0x00400000;
wdenkd4ca31c2004-01-02 14:00:00 +0000471 break; /* => 4 MB */
472
473 case AMD_ID_DL163B:
474 info->flash_id += FLASH_AMDL163B;
475 info->sector_count = 39;
476 info->size = 0x00400000;
477 break; /* => 4 MB */
wdenkf12e5682003-07-07 20:07:54 +0000478
wdenkc6097192002-11-03 00:24:07 +0000479 default:
480 info->flash_id = FLASH_UNKNOWN;
481 return (0); /* => no or unknown flash */
482 }
483
484 /* set up sector start address table */
485 switch (value) {
wdenk71f95112003-06-15 22:40:42 +0000486#ifdef CONFIG_TQM8xxM /* mirror bit flash */
487 case AMD_ID_MIRROR:
488 switch (info->flash_id & FLASH_TYPEMASK) {
489 /* only known types here - no default */
490 case FLASH_AMLV128U:
wdenkf12e5682003-07-07 20:07:54 +0000491 case FLASH_AMLV640U:
492 case FLASH_AMLV320U:
wdenk71f95112003-06-15 22:40:42 +0000493 for (i = 0; i < info->sector_count; i++) {
494 info->start[i] = base;
495 base += 0x20000;
496 }
497 break;
wdenkd4ca31c2004-01-02 14:00:00 +0000498 case FLASH_AMLV320B:
499 for (i = 0; i < info->sector_count; i++) {
500 info->start[i] = base;
501 /*
502 * The first 8 sectors are 8 kB,
503 * all the other ones are 64 kB
504 */
505 base += (i < 8)
506 ? 2 * ( 8 << 10)
507 : 2 * (64 << 10);
508 }
509 break;
wdenk71f95112003-06-15 22:40:42 +0000510 }
511 break;
512# else /* ! TQM8xxM */
wdenkc6097192002-11-03 00:24:07 +0000513 case AMD_ID_LV400B:
514 case AMD_ID_LV800B:
wdenkc6097192002-11-03 00:24:07 +0000515 /* set sector offsets for bottom boot block type */
516 info->start[0] = base + 0x00000000;
517 info->start[1] = base + 0x00008000;
518 info->start[2] = base + 0x0000C000;
519 info->start[3] = base + 0x00010000;
520 for (i = 4; i < info->sector_count; i++) {
521 info->start[i] = base + (i * 0x00020000) - 0x00060000;
522 }
523 break;
524 case AMD_ID_LV400T:
525 case AMD_ID_LV800T:
wdenkc6097192002-11-03 00:24:07 +0000526 /* set sector offsets for top boot block type */
527 i = info->sector_count - 1;
528 info->start[i--] = base + info->size - 0x00008000;
529 info->start[i--] = base + info->size - 0x0000C000;
530 info->start[i--] = base + info->size - 0x00010000;
531 for (; i >= 0; i--) {
532 info->start[i] = base + i * 0x00020000;
533 }
534 break;
535 case AMD_ID_LV320B:
536 for (i = 0; i < info->sector_count; i++) {
537 info->start[i] = base;
538 /*
539 * The first 8 sectors are 8 kB,
540 * all the other ones are 64 kB
541 */
542 base += (i < 8)
543 ? 2 * ( 8 << 10)
544 : 2 * (64 << 10);
545 }
546 break;
547 case AMD_ID_LV320T:
548 for (i = 0; i < info->sector_count; i++) {
549 info->start[i] = base;
550 /*
551 * The last 8 sectors are 8 kB,
552 * all the other ones are 64 kB
553 */
554 base += (i < (info->sector_count - 8))
555 ? 2 * (64 << 10)
556 : 2 * ( 8 << 10);
557 }
558 break;
wdenk71f95112003-06-15 22:40:42 +0000559#endif /* TQM8xxM */
wdenkf12e5682003-07-07 20:07:54 +0000560 case AMD_ID_LV160B:
561 /* set sector offsets for bottom boot block type */
562 info->start[0] = base + 0x00000000;
563 info->start[1] = base + 0x00008000;
564 info->start[2] = base + 0x0000C000;
565 info->start[3] = base + 0x00010000;
566 for (i = 4; i < info->sector_count; i++) {
567 info->start[i] = base + (i * 0x00020000) - 0x00060000;
568 }
569 break;
570 case AMD_ID_LV160T:
571 /* set sector offsets for top boot block type */
572 i = info->sector_count - 1;
573 info->start[i--] = base + info->size - 0x00008000;
574 info->start[i--] = base + info->size - 0x0000C000;
575 info->start[i--] = base + info->size - 0x00010000;
576 for (; i >= 0; i--) {
577 info->start[i] = base + i * 0x00020000;
578 }
579 break;
wdenkd4ca31c2004-01-02 14:00:00 +0000580 case AMD_ID_DL163B:
581 for (i = 0; i < info->sector_count; i++) {
582 info->start[i] = base;
583 /*
584 * The first 8 sectors are 8 kB,
585 * all the other ones are 64 kB
586 */
587 base += (i < 8)
588 ? 2 * ( 8 << 10)
589 : 2 * (64 << 10);
590 }
591 break;
wdenkc6097192002-11-03 00:24:07 +0000592 default:
593 return (0);
594 break;
595 }
596
wdenkd4ca31c2004-01-02 14:00:00 +0000597#if 0
wdenkc6097192002-11-03 00:24:07 +0000598 /* check for protected sectors */
599 for (i = 0; i < info->sector_count; i++) {
600 /* read sector protection at sector address, (A7 .. A0) = 0x02 */
601 /* D0 = 1 if protected */
602 addr = (volatile unsigned long *)(info->start[i]);
603 info->protect[i] = addr[2] & 1;
604 }
wdenkd4ca31c2004-01-02 14:00:00 +0000605#endif
wdenkc6097192002-11-03 00:24:07 +0000606
607 /*
608 * Prevent writes to uninitialized FLASH.
609 */
610 if (info->flash_id != FLASH_UNKNOWN) {
611 addr = (volatile unsigned long *)info->start[0];
612
613 *addr = 0x00F000F0; /* reset bank */
614 }
615
616 return (info->size);
617}
618
619
620/*-----------------------------------------------------------------------
621 */
622
623int flash_erase (flash_info_t *info, int s_first, int s_last)
624{
625 vu_long *addr = (vu_long*)(info->start[0]);
626 int flag, prot, sect, l_sect;
627 ulong start, now, last;
628
wdenk73a8b272003-06-05 19:27:42 +0000629 debug ("flash_erase: first: %d last: %d\n", s_first, s_last);
630
wdenkc6097192002-11-03 00:24:07 +0000631 if ((s_first < 0) || (s_first > s_last)) {
632 if (info->flash_id == FLASH_UNKNOWN) {
633 printf ("- missing\n");
634 } else {
635 printf ("- no sectors to erase\n");
636 }
637 return 1;
638 }
639
640 if ((info->flash_id == FLASH_UNKNOWN) ||
641 (info->flash_id > FLASH_AMD_COMP)) {
642 printf ("Can't erase unknown flash type %08lx - aborted\n",
643 info->flash_id);
644 return 1;
645 }
646
647 prot = 0;
648 for (sect=s_first; sect<=s_last; ++sect) {
649 if (info->protect[sect]) {
650 prot++;
651 }
652 }
653
654 if (prot) {
655 printf ("- Warning: %d protected sectors will not be erased!\n",
656 prot);
657 } else {
658 printf ("\n");
659 }
660
661 l_sect = -1;
662
663 /* Disable interrupts which might cause a timeout here */
664 flag = disable_interrupts();
665
666 addr[0x0555] = 0x00AA00AA;
667 addr[0x02AA] = 0x00550055;
668 addr[0x0555] = 0x00800080;
669 addr[0x0555] = 0x00AA00AA;
670 addr[0x02AA] = 0x00550055;
671
672 /* Start erase on unprotected sectors */
673 for (sect = s_first; sect<=s_last; sect++) {
674 if (info->protect[sect] == 0) { /* not protected */
675 addr = (vu_long*)(info->start[sect]);
676 addr[0] = 0x00300030;
677 l_sect = sect;
678 }
679 }
680
681 /* re-enable interrupts if necessary */
682 if (flag)
683 enable_interrupts();
684
685 /* wait at least 80us - let's wait 1 ms */
686 udelay (1000);
687
688 /*
689 * We wait for the last triggered sector
690 */
691 if (l_sect < 0)
692 goto DONE;
693
694 start = get_timer (0);
695 last = start;
696 addr = (vu_long*)(info->start[l_sect]);
697 while ((addr[0] & 0x00800080) != 0x00800080) {
698 if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
699 printf ("Timeout\n");
700 return 1;
701 }
702 /* show that we're waiting */
703 if ((now - last) > 1000) { /* every second */
704 putc ('.');
705 last = now;
706 }
707 }
708
709DONE:
710 /* reset to read mode */
711 addr = (volatile unsigned long *)info->start[0];
712 addr[0] = 0x00F000F0; /* reset bank */
713
714 printf (" done\n");
715 return 0;
716}
717
718/*-----------------------------------------------------------------------
719 * Copy memory to flash, returns:
720 * 0 - OK
721 * 1 - write timeout
722 * 2 - Flash not erased
723 */
724
725int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
726{
727 ulong cp, wp, data;
728 int i, l, rc;
729
730 wp = (addr & ~3); /* get lower word aligned address */
731
732 /*
733 * handle unaligned start bytes
734 */
735 if ((l = addr - wp) != 0) {
736 data = 0;
737 for (i=0, cp=wp; i<l; ++i, ++cp) {
738 data = (data << 8) | (*(uchar *)cp);
739 }
740 for (; i<4 && cnt>0; ++i) {
741 data = (data << 8) | *src++;
742 --cnt;
743 ++cp;
744 }
745 for (; cnt==0 && i<4; ++i, ++cp) {
746 data = (data << 8) | (*(uchar *)cp);
747 }
748
749 if ((rc = write_word(info, wp, data)) != 0) {
750 return (rc);
751 }
752 wp += 4;
753 }
754
755 /*
756 * handle word aligned part
757 */
758 while (cnt >= 4) {
759 data = 0;
760 for (i=0; i<4; ++i) {
761 data = (data << 8) | *src++;
762 }
763 if ((rc = write_word(info, wp, data)) != 0) {
764 return (rc);
765 }
766 wp += 4;
767 cnt -= 4;
768 }
769
770 if (cnt == 0) {
771 return (0);
772 }
773
774 /*
775 * handle unaligned tail bytes
776 */
777 data = 0;
778 for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
779 data = (data << 8) | *src++;
780 --cnt;
781 }
782 for (; i<4; ++i, ++cp) {
783 data = (data << 8) | (*(uchar *)cp);
784 }
785
786 return (write_word(info, wp, data));
787}
788
789/*-----------------------------------------------------------------------
790 * Write a word to Flash, returns:
791 * 0 - OK
792 * 1 - write timeout
793 * 2 - Flash not erased
794 */
795static int write_word (flash_info_t *info, ulong dest, ulong data)
796{
797 vu_long *addr = (vu_long*)(info->start[0]);
798 ulong start;
799 int flag;
800
801 /* Check if Flash is (sufficiently) erased */
802 if ((*((vu_long *)dest) & data) != data) {
803 return (2);
804 }
805 /* Disable interrupts which might cause a timeout here */
806 flag = disable_interrupts();
807
808 addr[0x0555] = 0x00AA00AA;
809 addr[0x02AA] = 0x00550055;
810 addr[0x0555] = 0x00A000A0;
811
812 *((vu_long *)dest) = data;
813
814 /* re-enable interrupts if necessary */
815 if (flag)
816 enable_interrupts();
817
818 /* data polling for D7 */
819 start = get_timer (0);
820 while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
821 if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
822 return (1);
823 }
824 }
825 return (0);
826}
827
828/*-----------------------------------------------------------------------
829 */