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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Bryan Wudf3443d2014-06-24 11:45:29 +09002/*
Alexandre Courbot871d78e2015-07-09 16:33:00 +09003 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
Bryan Wudf3443d2014-06-24 11:45:29 +09004 */
5
6/* Tegra vpr routines */
7
8#include <common.h>
9#include <asm/io.h>
10#include <asm/arch/tegra.h>
11#include <asm/arch/mc.h>
Stephen Warren3d186cf2018-07-31 12:39:07 -060012#include <asm/arch-tegra/ap.h>
Bryan Wudf3443d2014-06-24 11:45:29 +090013
Alexandre Courbot871d78e2015-07-09 16:33:00 +090014#include <fdt_support.h>
15
16static bool _configured;
17
Alexandre Courboteca676b2015-10-19 13:57:03 +090018void tegra_gpu_config(void)
Bryan Wudf3443d2014-06-24 11:45:29 +090019{
20 struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
21
Stephen Warren3d186cf2018-07-31 12:39:07 -060022#if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
23 if (!tegra_cpu_is_non_secure())
24#endif
25 {
26 /* Turn VPR off */
27 writel(0, &mc->mc_video_protect_size_mb);
28 writel(TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED,
29 &mc->mc_video_protect_reg_ctrl);
30 /* read back to ensure the write went through */
31 readl(&mc->mc_video_protect_reg_ctrl);
32 }
Alexandre Courbot871d78e2015-07-09 16:33:00 +090033
34 debug("configured VPR\n");
35
36 _configured = true;
37}
38
Alexandre Courbota38a3c42015-07-09 16:33:01 +090039#if defined(CONFIG_OF_LIBFDT)
40
Stephen Warrend9b6f582016-04-12 11:17:39 -060041int tegra_gpu_enable_node(void *blob, const char *compat)
Alexandre Courbota38a3c42015-07-09 16:33:01 +090042{
43 int offset;
44
Stephen Warrend9b6f582016-04-12 11:17:39 -060045 if (!_configured)
46 return 0;
47
48 offset = fdt_node_offset_by_compatible(blob, -1, compat);
49 while (offset != -FDT_ERR_NOTFOUND) {
50 fdt_status_okay(blob, offset);
51 offset = fdt_node_offset_by_compatible(blob, offset, compat);
Alexandre Courbota38a3c42015-07-09 16:33:01 +090052 }
53
54 return 0;
55}
56
57#endif