Sergey Temerkhanov | 746f985 | 2015-10-14 09:55:50 -0700 | [diff] [blame] | 1 | /** |
| 2 | * (C) Copyright 2014, Cavium Inc. |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | **/ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <malloc.h> |
| 9 | #include <errno.h> |
| 10 | #include <linux/compiler.h> |
| 11 | |
Sergey Temerkhanov | 3ed2ece | 2015-10-14 09:55:52 -0700 | [diff] [blame] | 12 | #include <cavium/atf.h> |
Alexander Graf | d473f0c | 2016-03-04 01:09:48 +0100 | [diff] [blame^] | 13 | #include <asm/armv8/mmu.h> |
Sergey Temerkhanov | 3ed2ece | 2015-10-14 09:55:52 -0700 | [diff] [blame] | 14 | |
Sergey Temerkhanov | 746f985 | 2015-10-14 09:55:50 -0700 | [diff] [blame] | 15 | #if !CONFIG_IS_ENABLED(OF_CONTROL) |
| 16 | #include <dm/platdata.h> |
| 17 | #include <dm/platform_data/serial_pl01x.h> |
| 18 | |
| 19 | static const struct pl01x_serial_platdata serial0 = { |
| 20 | .base = CONFIG_SYS_SERIAL0, |
| 21 | .type = TYPE_PL011, |
| 22 | .clock = 0, |
| 23 | .skip_init = true, |
| 24 | }; |
| 25 | |
| 26 | U_BOOT_DEVICE(thunderx_serial0) = { |
| 27 | .name = "serial_pl01x", |
| 28 | .platdata = &serial0, |
| 29 | }; |
| 30 | |
| 31 | static const struct pl01x_serial_platdata serial1 = { |
| 32 | .base = CONFIG_SYS_SERIAL1, |
| 33 | .type = TYPE_PL011, |
| 34 | .clock = 0, |
| 35 | .skip_init = true, |
| 36 | }; |
| 37 | |
| 38 | U_BOOT_DEVICE(thunderx_serial1) = { |
| 39 | .name = "serial_pl01x", |
| 40 | .platdata = &serial1, |
| 41 | }; |
| 42 | #endif |
| 43 | |
| 44 | DECLARE_GLOBAL_DATA_PTR; |
| 45 | |
Alexander Graf | d473f0c | 2016-03-04 01:09:48 +0100 | [diff] [blame^] | 46 | static struct mm_region thunderx_mem_map[] = { |
| 47 | { |
| 48 | .base = 0x000000000000UL, |
| 49 | .size = 0x40000000000UL, |
| 50 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE, |
| 51 | }, { |
| 52 | .base = 0x800000000000UL, |
| 53 | .size = 0x40000000000UL, |
| 54 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 55 | PTE_BLOCK_NON_SHARE, |
| 56 | }, { |
| 57 | .base = 0x840000000000UL, |
| 58 | .size = 0x40000000000UL, |
| 59 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 60 | PTE_BLOCK_NON_SHARE, |
| 61 | }, { |
| 62 | /* List terminator */ |
| 63 | 0, |
| 64 | } |
| 65 | }; |
| 66 | |
| 67 | struct mm_region *mem_map = thunderx_mem_map; |
| 68 | |
Sergey Temerkhanov | 746f985 | 2015-10-14 09:55:50 -0700 | [diff] [blame] | 69 | int board_init(void) |
| 70 | { |
| 71 | return 0; |
| 72 | } |
| 73 | |
| 74 | int timer_init(void) |
| 75 | { |
| 76 | return 0; |
| 77 | } |
| 78 | |
Sergey Temerkhanov | 3ed2ece | 2015-10-14 09:55:52 -0700 | [diff] [blame] | 79 | int dram_init(void) |
| 80 | { |
| 81 | ssize_t node_count = atf_node_count(); |
| 82 | ssize_t dram_size; |
| 83 | int node; |
| 84 | |
| 85 | printf("Initializing\nNodes in system: %zd\n", node_count); |
| 86 | |
| 87 | gd->ram_size = 0; |
| 88 | |
| 89 | for (node = 0; node < node_count; node++) { |
| 90 | dram_size = atf_dram_size(node); |
| 91 | printf("Node %d: %zd MBytes of DRAM\n", node, dram_size >> 20); |
| 92 | gd->ram_size += dram_size; |
| 93 | } |
| 94 | |
| 95 | gd->ram_size -= MEM_BASE; |
| 96 | |
| 97 | *(unsigned long *)CPU_RELEASE_ADDR = 0; |
| 98 | |
| 99 | puts("DRAM size:"); |
| 100 | |
| 101 | return 0; |
| 102 | } |
| 103 | |
Sergey Temerkhanov | 746f985 | 2015-10-14 09:55:50 -0700 | [diff] [blame] | 104 | /* |
| 105 | * Board specific reset that is system reset. |
| 106 | */ |
| 107 | void reset_cpu(ulong addr) |
| 108 | { |
| 109 | } |
| 110 | |
| 111 | /* |
| 112 | * Board specific ethernet initialization routine. |
| 113 | */ |
| 114 | int board_eth_init(bd_t *bis) |
| 115 | { |
| 116 | int rc = 0; |
| 117 | |
| 118 | return rc; |
| 119 | } |
| 120 | |
| 121 | #ifdef CONFIG_PCI |
| 122 | void pci_init_board(void) |
| 123 | { |
| 124 | printf("DEBUG: PCI Init TODO *****\n"); |
| 125 | } |
| 126 | #endif |