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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +09002
Tom Rinid678a592024-05-18 20:20:43 -06003#include <common.h>
Simon Glass9a3b4ce2019-12-28 10:45:01 -07004#include <cpu_func.h>
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +09005#include <asm/processor.h>
Nobuhiro Iwamatsu754613f2010-06-16 16:55:26 +09006#include <asm/system.h>
Nobuhiro Iwamatsu4a065ab2008-09-18 19:04:26 +09007#include <asm/io.h>
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +09008
9#define WDT_BASE WTCNT
10
Nobuhiro Iwamatsu4a065ab2008-09-18 19:04:26 +090011#define WDT_WD (1 << 6)
12#define WDT_RST_P (0)
13#define WDT_RST_M (1 << 5)
14#define WDT_ENABLE (1 << 7)
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +090015
Nobuhiro Iwamatsu4a065ab2008-09-18 19:04:26 +090016#if defined(CONFIG_WATCHDOG)
17static unsigned char csr_read(void)
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +090018{
Nobuhiro Iwamatsu4a065ab2008-09-18 19:04:26 +090019 return inb(WDT_BASE + 0x04);
20}
21
22static void cnt_write(unsigned char value)
23{
24 outl((unsigned short)value | 0x5A00, WDT_BASE + 0x00);
25}
26
27static void csr_write(unsigned char value)
28{
29 outl((unsigned short)value | 0xA500, WDT_BASE + 0x04);
30}
31
32void watchdog_reset(void)
33{
34 outl(0x55000000, WDT_BASE + 0x08);
35}
36
37int watchdog_init(void)
38{
39 /* Set overflow time*/
40 cnt_write(0);
41 /* Power on reset */
42 csr_write(WDT_WD|WDT_RST_P|WDT_ENABLE);
43
44 return 0;
45}
46
47int watchdog_disable(void)
48{
49 csr_write(csr_read() & ~WDT_ENABLE);
50 return 0;
51}
52#endif
53
Harald Seiler35b65dd2020-12-15 16:47:52 +010054void reset_cpu(void)
Nobuhiro Iwamatsu4a065ab2008-09-18 19:04:26 +090055{
Nobuhiro Iwamatsu754613f2010-06-16 16:55:26 +090056 /* Address error with SR.BL=1 first. */
57 trigger_address_error();
58
Nobuhiro Iwamatsu4a065ab2008-09-18 19:04:26 +090059 while (1)
60 ;
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +090061}