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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / d47c4fea8c22d8b5dc16ad3def2877ea15ae4289 / . / drivers / clk / sunxi / clk_a83t.c
blob: 8c6043f51e2687585b6e932d1e599e7d2fd69b67 [file] [log] [blame]
Jagan Teki03d87f52018-08-02 23:33:55 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 Amarula Solutions.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <errno.h>
Samuel Holland21d314a2021-09-12 11:48:43 -0500[diff] [blame]11#include <clk/sunxi.h>
Jagan Teki03d87f52018-08-02 23:33:55 +0530[diff] [blame]12#include <dt-bindings/clock/sun8i-a83t-ccu.h>
13#include <dt-bindings/reset/sun8i-a83t-ccu.h>
Simon Glasscd93d622020-05-10 11:40:13 -0600[diff] [blame]14#include <linux/bitops.h>
Jagan Teki03d87f52018-08-02 23:33:55 +0530[diff] [blame]15
16static struct ccu_clk_gate a83t_gates[] = {
Andre Przywarabb3e5aa2019-01-29 15:54:09 +0000[diff] [blame]17 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
18 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
19 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
Jagan Teki68620c92019-02-28 00:26:57 +0530[diff] [blame]20 [CLK_BUS_EMAC] = GATE(0x060, BIT(17)),
Jagan Teki82111462019-02-27 20:02:06 +0530[diff] [blame]21 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
22 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
Jagan Teki03d87f52018-08-02 23:33:55 +0530[diff] [blame]23 [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
24 [CLK_BUS_EHCI0] = GATE(0x060, BIT(26)),
25 [CLK_BUS_EHCI1] = GATE(0x060, BIT(27)),
26 [CLK_BUS_OHCI0] = GATE(0x060, BIT(29)),
27
Samuel Hollandc61897b2021-09-12 09:47:24 -0500[diff] [blame]28 [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
29 [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
30 [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
Jagan Teki4acc7112018-12-30 21:29:24 +0530[diff] [blame]31 [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
32 [CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
33 [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
34 [CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
35 [CLK_BUS_UART4] = GATE(0x06c, BIT(20)),
36
Jagan Teki82111462019-02-27 20:02:06 +0530[diff] [blame]37 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
38 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
39
Jagan Teki03d87f52018-08-02 23:33:55 +0530[diff] [blame]40 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
41 [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
42 [CLK_USB_HSIC] = GATE(0x0cc, BIT(10)),
43 [CLK_USB_HSIC_12M] = GATE(0x0cc, BIT(11)),
44 [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)),
45};
46
47static struct ccu_reset a83t_resets[] = {
48 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
49 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
50 [RST_USB_HSIC] = RESET(0x0cc, BIT(2)),
51
Andre Przywarabb3e5aa2019-01-29 15:54:09 +0000[diff] [blame]52 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
53 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
54 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
Jagan Teki68620c92019-02-28 00:26:57 +0530[diff] [blame]55 [RST_BUS_EMAC] = RESET(0x2c0, BIT(17)),
Jagan Teki82111462019-02-27 20:02:06 +0530[diff] [blame]56 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
57 [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
Jagan Teki03d87f52018-08-02 23:33:55 +0530[diff] [blame]58 [RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
59 [RST_BUS_EHCI0] = RESET(0x2c0, BIT(26)),
60 [RST_BUS_EHCI1] = RESET(0x2c0, BIT(27)),
61 [RST_BUS_OHCI0] = RESET(0x2c0, BIT(29)),
Jagan Teki8606f962018-12-30 21:37:31 +0530[diff] [blame]62
Samuel Hollandc61897b2021-09-12 09:47:24 -0500[diff] [blame]63 [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
64 [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
65 [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)),
Jagan Teki8606f962018-12-30 21:37:31 +0530[diff] [blame]66 [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
67 [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
68 [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
69 [RST_BUS_UART3] = RESET(0x2d8, BIT(19)),
70 [RST_BUS_UART4] = RESET(0x2d8, BIT(20)),
Jagan Teki03d87f52018-08-02 23:33:55 +0530[diff] [blame]71};
72
73static const struct ccu_desc a83t_ccu_desc = {
74 .gates = a83t_gates,
75 .resets = a83t_resets,
76};
77
78static int a83t_clk_bind(struct udevice *dev)
79{
80 return sunxi_reset_bind(dev, ARRAY_SIZE(a83t_resets));
81}
82
83static const struct udevice_id a83t_clk_ids[] = {
84 { .compatible = "allwinner,sun8i-a83t-ccu",
85 .data = (ulong)&a83t_ccu_desc },
86 { }
87};
88
89U_BOOT_DRIVER(clk_sun8i_a83t) = {
90 .name = "sun8i_a83t_ccu",
91 .id = UCLASS_CLK,
92 .of_match = a83t_clk_ids,
Simon Glass41575d82020-12-03 16:55:17 -0700[diff] [blame]93 .priv_auto = sizeof(struct ccu_priv),
Jagan Teki03d87f52018-08-02 23:33:55 +0530[diff] [blame]94 .ops = &sunxi_clk_ops,
95 .probe = sunxi_clk_probe,
96 .bind = a83t_clk_bind,
97};