Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Stelian Pop | d99a8ff | 2008-05-08 20:52:22 +0200 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2007-2008 |
Stelian Pop | c9e798d | 2011-11-01 00:00:39 +0100 | [diff] [blame] | 4 | * Stelian Pop <stelian@popies.net> |
Stelian Pop | d99a8ff | 2008-05-08 20:52:22 +0200 | [diff] [blame] | 5 | * Lead Tech Design <www.leadtechdesign.com> |
| 6 | * |
| 7 | * Configuation settings for the AT91SAM9261EK board. |
Stelian Pop | d99a8ff | 2008-05-08 20:52:22 +0200 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #ifndef __CONFIG_H |
| 11 | #define __CONFIG_H |
| 12 | |
| 13 | /* ARM asynchronous clock */ |
Xu, Hong | f7aea46 | 2011-07-31 22:49:00 +0000 | [diff] [blame] | 14 | #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ |
Achim Ehrlich | 7c966a8 | 2010-02-24 10:29:16 +0100 | [diff] [blame] | 15 | #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ |
Stelian Pop | d99a8ff | 2008-05-08 20:52:22 +0200 | [diff] [blame] | 16 | |
Xu, Hong | f7aea46 | 2011-07-31 22:49:00 +0000 | [diff] [blame] | 17 | #ifdef CONFIG_AT91SAM9G10 |
| 18 | #define CONFIG_AT91SAM9G10EK /* It's an Atmel AT91SAM9G10 EK*/ |
Sedji Gaouaou | 5ccc2d9 | 2009-06-25 17:04:15 +0200 | [diff] [blame] | 19 | #else |
Xu, Hong | f7aea46 | 2011-07-31 22:49:00 +0000 | [diff] [blame] | 20 | #define CONFIG_AT91SAM9261EK /* It's an Atmel AT91SAM9261 EK*/ |
Sedji Gaouaou | 5ccc2d9 | 2009-06-25 17:04:15 +0200 | [diff] [blame] | 21 | #endif |
Xu, Hong | f7aea46 | 2011-07-31 22:49:00 +0000 | [diff] [blame] | 22 | |
| 23 | #include <asm/hardware.h> |
| 24 | |
Xu, Hong | f7aea46 | 2011-07-31 22:49:00 +0000 | [diff] [blame] | 25 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
| 26 | #define CONFIG_SETUP_MEMORY_TAGS |
| 27 | #define CONFIG_INITRD_TAG |
Stelian Pop | d99a8ff | 2008-05-08 20:52:22 +0200 | [diff] [blame] | 28 | |
| 29 | #define CONFIG_SKIP_LOWLEVEL_INIT |
Stelian Pop | d99a8ff | 2008-05-08 20:52:22 +0200 | [diff] [blame] | 30 | |
Xu, Hong | f7aea46 | 2011-07-31 22:49:00 +0000 | [diff] [blame] | 31 | #define CONFIG_ATMEL_LEGACY |
Xu, Hong | f7aea46 | 2011-07-31 22:49:00 +0000 | [diff] [blame] | 32 | |
Stelian Pop | d99a8ff | 2008-05-08 20:52:22 +0200 | [diff] [blame] | 33 | /* |
| 34 | * Hardware drivers |
| 35 | */ |
Xu, Hong | f7aea46 | 2011-07-31 22:49:00 +0000 | [diff] [blame] | 36 | |
Stelian Pop | 820f2a9 | 2008-05-08 14:52:30 +0200 | [diff] [blame] | 37 | /* LCD */ |
Stelian Pop | 820f2a9 | 2008-05-08 14:52:30 +0200 | [diff] [blame] | 38 | #define LCD_BPP LCD_COLOR8 |
Xu, Hong | f7aea46 | 2011-07-31 22:49:00 +0000 | [diff] [blame] | 39 | #define CONFIG_LCD_LOGO |
Stelian Pop | 820f2a9 | 2008-05-08 14:52:30 +0200 | [diff] [blame] | 40 | #undef LCD_TEST_PATTERN |
Xu, Hong | f7aea46 | 2011-07-31 22:49:00 +0000 | [diff] [blame] | 41 | #define CONFIG_LCD_INFO |
| 42 | #define CONFIG_LCD_INFO_BELOW_LOGO |
Xu, Hong | f7aea46 | 2011-07-31 22:49:00 +0000 | [diff] [blame] | 43 | #define CONFIG_ATMEL_LCD |
Sedji Gaouaou | 5ccc2d9 | 2009-06-25 17:04:15 +0200 | [diff] [blame] | 44 | #ifdef CONFIG_AT91SAM9261EK |
Xu, Hong | f7aea46 | 2011-07-31 22:49:00 +0000 | [diff] [blame] | 45 | #define CONFIG_ATMEL_LCD_BGR555 |
Sedji Gaouaou | 5ccc2d9 | 2009-06-25 17:04:15 +0200 | [diff] [blame] | 46 | #endif |
Xu, Hong | f7aea46 | 2011-07-31 22:49:00 +0000 | [diff] [blame] | 47 | |
Stelian Pop | d99a8ff | 2008-05-08 20:52:22 +0200 | [diff] [blame] | 48 | /* |
| 49 | * BOOTP options |
| 50 | */ |
Xu, Hong | f7aea46 | 2011-07-31 22:49:00 +0000 | [diff] [blame] | 51 | #define CONFIG_BOOTP_BOOTFILESIZE |
Stelian Pop | d99a8ff | 2008-05-08 20:52:22 +0200 | [diff] [blame] | 52 | |
Stelian Pop | d99a8ff | 2008-05-08 20:52:22 +0200 | [diff] [blame] | 53 | /* SDRAM */ |
Xu, Hong | f7aea46 | 2011-07-31 22:49:00 +0000 | [diff] [blame] | 54 | #define CONFIG_SYS_SDRAM_BASE 0x20000000 |
| 55 | #define CONFIG_SYS_SDRAM_SIZE 0x04000000 |
| 56 | #define CONFIG_SYS_INIT_SP_ADDR \ |
Wenyou.Yang@microchip.com | 324873e | 2017-07-21 13:28:40 +0800 | [diff] [blame] | 57 | (ATMEL_BASE_SRAM + 16 * 1024 - GENERATED_GBL_DATA_SIZE) |
Stelian Pop | d99a8ff | 2008-05-08 20:52:22 +0200 | [diff] [blame] | 58 | |
| 59 | /* NAND flash */ |
Jean-Christophe PLAGNIOL-VILLARD | 74c076d | 2009-03-22 10:22:34 +0100 | [diff] [blame] | 60 | #ifdef CONFIG_CMD_NAND |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 61 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| 62 | #define CONFIG_SYS_NAND_BASE 0x40000000 |
Xu, Hong | f7aea46 | 2011-07-31 22:49:00 +0000 | [diff] [blame] | 63 | #define CONFIG_SYS_NAND_DBW_8 |
Jean-Christophe PLAGNIOL-VILLARD | 74c076d | 2009-03-22 10:22:34 +0100 | [diff] [blame] | 64 | /* our ALE is AD22 */ |
| 65 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 22) |
| 66 | /* our CLE is AD21 */ |
| 67 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 21) |
| 68 | #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 |
| 69 | #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC15 |
Wolfgang Denk | 2eb99ca | 2009-07-18 21:52:24 +0200 | [diff] [blame] | 70 | |
Jean-Christophe PLAGNIOL-VILLARD | 74c076d | 2009-03-22 10:22:34 +0100 | [diff] [blame] | 71 | #endif |
Stelian Pop | d99a8ff | 2008-05-08 20:52:22 +0200 | [diff] [blame] | 72 | |
Stelian Pop | d99a8ff | 2008-05-08 20:52:22 +0200 | [diff] [blame] | 73 | /* Ethernet */ |
Xu, Hong | f7aea46 | 2011-07-31 22:49:00 +0000 | [diff] [blame] | 74 | #define CONFIG_DRIVER_DM9000 |
Stelian Pop | d99a8ff | 2008-05-08 20:52:22 +0200 | [diff] [blame] | 75 | #define CONFIG_DM9000_BASE 0x30000000 |
| 76 | #define DM9000_IO CONFIG_DM9000_BASE |
| 77 | #define DM9000_DATA (CONFIG_DM9000_BASE + 4) |
Xu, Hong | f7aea46 | 2011-07-31 22:49:00 +0000 | [diff] [blame] | 78 | #define CONFIG_DM9000_USE_16BIT |
| 79 | #define CONFIG_DM9000_NO_SROM |
Stelian Pop | d99a8ff | 2008-05-08 20:52:22 +0200 | [diff] [blame] | 80 | #define CONFIG_NET_RETRY_COUNT 20 |
Xu, Hong | f7aea46 | 2011-07-31 22:49:00 +0000 | [diff] [blame] | 81 | #define CONFIG_RESET_PHY_R |
Stelian Pop | d99a8ff | 2008-05-08 20:52:22 +0200 | [diff] [blame] | 82 | |
| 83 | /* USB */ |
Jean-Christophe PLAGNIOL-VILLARD | 2b7178a | 2009-03-27 23:26:44 +0100 | [diff] [blame] | 84 | #define CONFIG_USB_ATMEL |
Bo Shen | dcd2f1a | 2013-10-21 16:14:00 +0800 | [diff] [blame] | 85 | #define CONFIG_USB_ATMEL_CLK_SEL_PLLB |
Xu, Hong | f7aea46 | 2011-07-31 22:49:00 +0000 | [diff] [blame] | 86 | #define CONFIG_USB_OHCI_NEW |
Xu, Hong | f7aea46 | 2011-07-31 22:49:00 +0000 | [diff] [blame] | 87 | #define CONFIG_SYS_USB_OHCI_CPU_INIT |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 88 | #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */ |
Sedji Gaouaou | 5ccc2d9 | 2009-06-25 17:04:15 +0200 | [diff] [blame] | 89 | #ifdef CONFIG_AT91SAM9G10EK |
| 90 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g10" |
| 91 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 92 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261" |
Sedji Gaouaou | 5ccc2d9 | 2009-06-25 17:04:15 +0200 | [diff] [blame] | 93 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 94 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 |
Stelian Pop | d99a8ff | 2008-05-08 20:52:22 +0200 | [diff] [blame] | 95 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 96 | #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ |
Stelian Pop | d99a8ff | 2008-05-08 20:52:22 +0200 | [diff] [blame] | 97 | |
Xu, Hong | f7aea46 | 2011-07-31 22:49:00 +0000 | [diff] [blame] | 98 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 99 | #define CONFIG_SYS_MEMTEST_END 0x23e00000 |
Stelian Pop | d99a8ff | 2008-05-08 20:52:22 +0200 | [diff] [blame] | 100 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 101 | #ifdef CONFIG_SYS_USE_DATAFLASH_CS0 |
Stelian Pop | d99a8ff | 2008-05-08 20:52:22 +0200 | [diff] [blame] | 102 | |
| 103 | /* bootstrap + u-boot + env + linux in dataflash on CS0 */ |
Nicolas Ferre | 89a7a87 | 2008-12-06 13:11:14 +0100 | [diff] [blame] | 104 | #define CONFIG_ENV_OFFSET 0x4200 |
Jean-Christophe PLAGNIOL-VILLARD | 0e8d158 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 105 | #define CONFIG_ENV_SIZE 0x4200 |
Wenyou.Yang@microchip.com | 324873e | 2017-07-21 13:28:40 +0800 | [diff] [blame] | 106 | #define CONFIG_ENV_SECT_SIZE 0x210 |
Wenyou.Yang@microchip.com | 324873e | 2017-07-21 13:28:40 +0800 | [diff] [blame] | 107 | #define CONFIG_BOOTCOMMAND "sf probe 0; " \ |
| 108 | "sf read 0x22000000 0x84000 0x294000; " \ |
| 109 | "bootm 0x22000000" |
Stelian Pop | d99a8ff | 2008-05-08 20:52:22 +0200 | [diff] [blame] | 110 | |
Nicolas Ferre | 89a7a87 | 2008-12-06 13:11:14 +0100 | [diff] [blame] | 111 | #elif CONFIG_SYS_USE_DATAFLASH_CS3 |
| 112 | |
| 113 | /* bootstrap + u-boot + env + linux in dataflash on CS3 */ |
Nicolas Ferre | 89a7a87 | 2008-12-06 13:11:14 +0100 | [diff] [blame] | 114 | #define CONFIG_ENV_OFFSET 0x4200 |
Nicolas Ferre | 89a7a87 | 2008-12-06 13:11:14 +0100 | [diff] [blame] | 115 | #define CONFIG_ENV_SIZE 0x4200 |
Wenyou.Yang@microchip.com | 324873e | 2017-07-21 13:28:40 +0800 | [diff] [blame] | 116 | #define CONFIG_ENV_SECT_SIZE 0x210 |
Wenyou.Yang@microchip.com | 324873e | 2017-07-21 13:28:40 +0800 | [diff] [blame] | 117 | #define CONFIG_BOOTCOMMAND "sf probe 0:3; " \ |
| 118 | "sf read 0x22000000 0x84000 0x294000; " \ |
| 119 | "bootm 0x22000000" |
Nicolas Ferre | 89a7a87 | 2008-12-06 13:11:14 +0100 | [diff] [blame] | 120 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 121 | #else /* CONFIG_SYS_USE_NANDFLASH */ |
Stelian Pop | d99a8ff | 2008-05-08 20:52:22 +0200 | [diff] [blame] | 122 | |
| 123 | /* bootstrap + u-boot + env + linux in nandflash */ |
Nicolas Ferre | 7b8b19f | 2018-05-09 10:30:25 +0300 | [diff] [blame] | 124 | #define CONFIG_ENV_OFFSET 0x140000 |
Bo Shen | 0c58cfa | 2013-02-20 00:16:25 +0000 | [diff] [blame] | 125 | #define CONFIG_ENV_OFFSET_REDUND 0x100000 |
Jean-Christophe PLAGNIOL-VILLARD | 0e8d158 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 126 | #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ |
Bo Shen | 0c58cfa | 2013-02-20 00:16:25 +0000 | [diff] [blame] | 127 | #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" |
Stelian Pop | d99a8ff | 2008-05-08 20:52:22 +0200 | [diff] [blame] | 128 | #endif |
| 129 | |
Stelian Pop | d99a8ff | 2008-05-08 20:52:22 +0200 | [diff] [blame] | 130 | /* |
| 131 | * Size of malloc() pool |
| 132 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 133 | #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) |
Stelian Pop | d99a8ff | 2008-05-08 20:52:22 +0200 | [diff] [blame] | 134 | |
Stelian Pop | d99a8ff | 2008-05-08 20:52:22 +0200 | [diff] [blame] | 135 | #endif |