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wdenk5b845b62002-08-21 21:57:24 +00001/*
wdenk5da627a2003-10-09 20:09:04 +00002 * (C) Copyright 2003
3 * Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de
4 *
wdenk5b845b62002-08-21 21:57:24 +00005 * (C) Copyright 2002
6 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 *
26 */
27
28/*
wdenk5b845b62002-08-21 21:57:24 +000029 * Altera FPGA support
30 */
31#include <common.h>
wdenk5da627a2003-10-09 20:09:04 +000032#include <ACEX1K.h>
wdenk5b845b62002-08-21 21:57:24 +000033
wdenk5da627a2003-10-09 20:09:04 +000034/* Define FPGA_DEBUG to get debug printf's */
35/* #define FPGA_DEBUG */
wdenk5b845b62002-08-21 21:57:24 +000036
37#ifdef FPGA_DEBUG
38#define PRINTF(fmt,args...) printf (fmt ,##args)
39#else
40#define PRINTF(fmt,args...)
41#endif
42
43#if (CONFIG_FPGA & CFG_FPGA_ALTERA)
44
wdenk5da627a2003-10-09 20:09:04 +000045/* Local Static Functions */
46static int altera_validate (Altera_desc * desc, char *fn);
47
wdenk5b845b62002-08-21 21:57:24 +000048/* ------------------------------------------------------------------------- */
49int altera_load( Altera_desc *desc, void *buf, size_t bsize )
50{
wdenk5da627a2003-10-09 20:09:04 +000051 int ret_val = FPGA_FAIL; /* assume a failure */
52
53 if (!altera_validate (desc, __FUNCTION__)) {
54 printf ("%s: Invalid device descriptor\n", __FUNCTION__);
55 } else {
56 switch (desc->family) {
57 case Altera_ACEX1K:
58#if (CONFIG_FPGA & CFG_ACEX1K)
59 PRINTF ("%s: Launching the ACEX1K Loader...\n",
60 __FUNCTION__);
61 ret_val = ACEX1K_load (desc, buf, bsize);
62#else
63 printf ("%s: No support for ACEX1K devices.\n",
64 __FUNCTION__);
65#endif
66 break;
67
68 default:
69 printf ("%s: Unsupported family type, %d\n",
70 __FUNCTION__, desc->family);
71 }
72 }
73
74 return ret_val;
wdenk5b845b62002-08-21 21:57:24 +000075}
76
77int altera_dump( Altera_desc *desc, void *buf, size_t bsize )
78{
wdenk5da627a2003-10-09 20:09:04 +000079 int ret_val = FPGA_FAIL; /* assume a failure */
80
81 if (!altera_validate (desc, __FUNCTION__)) {
82 printf ("%s: Invalid device descriptor\n", __FUNCTION__);
83 } else {
84 switch (desc->family) {
85 case Altera_ACEX1K:
86#if (CONFIG_FPGA & CFG_ACEX)
87 PRINTF ("%s: Launching the ACEX1K Reader...\n",
88 __FUNCTION__);
89 ret_val = ACEX1K_dump (desc, buf, bsize);
90#else
91 printf ("%s: No support for ACEX1K devices.\n",
92 __FUNCTION__);
93#endif
94 break;
95
96 default:
97 printf ("%s: Unsupported family type, %d\n",
98 __FUNCTION__, desc->family);
99 }
100 }
101
102 return ret_val;
wdenk5b845b62002-08-21 21:57:24 +0000103}
104
105int altera_info( Altera_desc *desc )
106{
wdenk5da627a2003-10-09 20:09:04 +0000107 int ret_val = FPGA_FAIL;
108
109 if (altera_validate (desc, __FUNCTION__)) {
110 printf ("Family: \t");
111 switch (desc->family) {
112 case Altera_ACEX1K:
113 printf ("ACEX1K\n");
114 break;
115 /* Add new family types here */
116 default:
117 printf ("Unknown family type, %d\n", desc->family);
118 }
119
120 printf ("Interface type:\t");
121 switch (desc->iface) {
122 case passive_serial:
123 printf ("Passive Serial (PS)\n");
124 break;
125 case passive_parallel_synchronous:
126 printf ("Passive Parallel Synchronous (PPS)\n");
127 break;
128 case passive_parallel_asynchronous:
129 printf ("Passive Parallel Asynchronous (PPA)\n");
130 break;
131 case passive_serial_asynchronous:
132 printf ("Passive Serial Asynchronous (PSA)\n");
133 break;
134 case altera_jtag_mode: /* Not used */
135 printf ("JTAG Mode\n");
136 break;
137 /* Add new interface types here */
138 default:
139 printf ("Unsupported interface type, %d\n", desc->iface);
140 }
141
142 printf ("Device Size: \t%d bytes\n"
143 "Cookie: \t0x%x (%d)\n",
144 desc->size, desc->cookie, desc->cookie);
145
146 if (desc->iface_fns) {
147 printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
148 switch (desc->family) {
149 case Altera_ACEX1K:
150#if (CONFIG_FPGA & CFG_ACEX1K)
151 ACEX1K_info (desc);
152#else
153 /* just in case */
154 printf ("%s: No support for ACEX1K devices.\n",
155 __FUNCTION__);
156#endif
157 break;
158 /* Add new family types here */
159 default:
160 /* we don't need a message here - we give one up above */
161 }
162 } else {
163 printf ("No Device Function Table.\n");
164 }
165
166 ret_val = FPGA_SUCCESS;
167 } else {
168 printf ("%s: Invalid device descriptor\n", __FUNCTION__);
169 }
170
171 return ret_val;
172}
173
174int altera_reloc( Altera_desc *desc, ulong reloc_offset)
175{
176 int ret_val = FPGA_FAIL; /* assume a failure */
177
178 if (!altera_validate (desc, __FUNCTION__)) {
179 printf ("%s: Invalid device descriptor\n", __FUNCTION__);
180 } else {
181 switch (desc->family) {
182 case Altera_ACEX1K:
183#if (CONFIG_FPGA & CFG_ACEX1K)
184 ret_val = ACEX1K_reloc (desc, reloc_offset);
185#else
186 printf ("%s: No support for ACEX devices.\n",
187 __FUNCTION__);
188#endif
189 break;
190 /* Add new family types here */
191 default:
192 printf ("%s: Unsupported family type, %d\n",
193 __FUNCTION__, desc->family);
194 }
195 }
196
197 return ret_val;
wdenk5b845b62002-08-21 21:57:24 +0000198}
199
200/* ------------------------------------------------------------------------- */
201
wdenk5da627a2003-10-09 20:09:04 +0000202static int altera_validate (Altera_desc * desc, char *fn)
203{
204 int ret_val = FALSE;
205
206 if (desc) {
207 if ((desc->family > min_altera_type) &&
208 (desc->family < max_altera_type)) {
209 if ((desc->iface > min_altera_iface_type) &&
210 (desc->iface < max_altera_iface_type)) {
211 if (desc->size) {
212 ret_val = TRUE;
213 } else {
214 printf ("%s: NULL part size\n", fn);
215 }
216 } else {
217 printf ("%s: Invalid Interface type, %d\n",
218 fn, desc->iface);
219 }
220 } else {
221 printf ("%s: Invalid family type, %d\n", fn, desc->family);
222 }
223 } else {
224 printf ("%s: NULL descriptor!\n", fn);
225 }
226
227 return ret_val;
228}
wdenk5b845b62002-08-21 21:57:24 +0000229
230/* ------------------------------------------------------------------------- */
231
wdenk5da627a2003-10-09 20:09:04 +0000232#endif /* CONFIG_FPGA & CFG_FPGA_ALTERA */