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Stefan Roese566806c2007-10-05 17:11:30 +02001/*
2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/************************************************************************
25 * kilauea.h - configuration for AMCC Kilauea (405EX)
26 ***********************************************************************/
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*-----------------------------------------------------------------------
32 * High Level Configuration Options
33 *----------------------------------------------------------------------*/
34#define CONFIG_KILAUEA 1 /* Board is Kilauea */
35#define CONFIG_4xx 1 /* ... PPC4xx family */
36#define CONFIG_405EX 1 /* Specifc 405EX support*/
37#define CONFIG_SYS_CLK_FREQ 33333333 /* ext frequency to pll */
38
39#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
40#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
41
42/*-----------------------------------------------------------------------
43 * Base addresses -- Note these are effective addresses where the
44 * actual resources get mapped (not physical addresses)
45 *----------------------------------------------------------------------*/
46#define CFG_SDRAM_BASE 0x00000000
47#define CFG_FLASH_BASE 0xFC000000
48#define CFG_NAND_ADDR 0xF8000000
49#define CFG_FPGA_BASE 0xF0000000
50#define CFG_PERIPHERAL_BASE 0xEF600000 /* internal peripherals*/
51#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
52#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
53#define CFG_MONITOR_BASE (TEXT_BASE)
54
55/*-----------------------------------------------------------------------
56 * Initial RAM & stack pointer
57 *----------------------------------------------------------------------*/
58#define CFG_INIT_RAM_ADDR 0x02000000 /* inside of SDRAM */
59#define CFG_INIT_RAM_END (4 << 10)
60#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
61#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
62/* reserve some memory for POST and BOOT limit info */
63#define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - 16)
64
65/* extra data in init-ram */
66#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 4)
67#define CFG_POST_MAGIC (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 8)
68#define CFG_POST_VAL (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET - 12)
69#define CFG_OCM_DATA_ADDR CFG_INIT_RAM_ADDR /* for commproc.c */
70
71/*-----------------------------------------------------------------------
72 * Serial Port
73 *----------------------------------------------------------------------*/
74#define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
75#define CONFIG_BAUDRATE 115200
76#define CONFIG_SERIAL_MULTI 1
77/* define this if you want console on UART1 */
78#undef CONFIG_UART1_CONSOLE
79
80#define CFG_BAUDRATE_TABLE \
81 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
82
83/*-----------------------------------------------------------------------
84 * Environment
85 *----------------------------------------------------------------------*/
86#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
87#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
88#else
89#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
90#define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */
91#endif
92
93/*-----------------------------------------------------------------------
94 * FLASH related
95 *----------------------------------------------------------------------*/
96#define CFG_FLASH_CFI /* The flash is CFI compatible */
97#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
98
99#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
100#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
101#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
102
103#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
104#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
105
106#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
107#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
108
109#ifdef CFG_ENV_IS_IN_FLASH
110#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
111#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
112#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
113
114/* Address and size of Redundant Environment Sector */
115#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
116#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
117#endif /* CFG_ENV_IS_IN_FLASH */
118
119/*-----------------------------------------------------------------------
120 * DDR SDRAM
121 *----------------------------------------------------------------------*/
122#define CFG_MBYTES_SDRAM (256) /* 256MB */
123
124/*-----------------------------------------------------------------------
125 * I2C
126 *----------------------------------------------------------------------*/
127#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
128#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
129#define CFG_I2C_SLAVE 0x7F
130
131#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
132#define CFG_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */
133#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
134
135/* Standard DTT sensor configuration */
136#define CONFIG_DTT_DS1775 1
137#define CONFIG_DTT_SENSORS { 0 }
138#define CFG_I2C_DTT_ADDR 0x48
139
140/* RTC configuration */
141#define CONFIG_RTC_DS1338 1
142#define CFG_I2C_RTC_ADDR 0x68
143
144/*-----------------------------------------------------------------------
145 * Ethernet
146 *----------------------------------------------------------------------*/
147#define CONFIG_M88E1111_PHY 1
148#define CONFIG_IBM_EMAC4_V4 1
149#define CONFIG_MII 1 /* MII PHY management */
150#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
151
152#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
153#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
154
155#define CONFIG_HAS_ETH0 1
156
157#define CONFIG_NET_MULTI 1
158#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
159#define CONFIG_PHY1_ADDR 2
160
161#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
162
163#define CONFIG_PREBOOT "echo;" \
164 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
165 "echo"
166
167#undef CONFIG_BOOTARGS
168
Stefan Roese566806c2007-10-05 17:11:30 +0200169#define CONFIG_EXTRA_ENV_SETTINGS \
170 "logversion=2\0" \
171 "netdev=eth0\0" \
172 "hostname=kilauea\0" \
173 "nfsargs=setenv bootargs root=/dev/nfs rw " \
174 "nfsroot=${serverip}:${rootpath}\0" \
175 "ramargs=setenv bootargs root=/dev/ram rw\0" \
176 "addip=setenv bootargs ${bootargs} " \
177 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
178 ":${hostname}:${netdev}:off panic=1\0" \
179 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
180 "net_nfs=tftp 200000 ${bootfile};" \
Stefan Roesefd671802007-10-11 11:15:59 +0200181 "run nfsargs addip addtty;" \
182 "bootm 200000\0" \
183 "net_nfs_fdt=tftp 200000 ${bootfile};" \
Stefan Roese566806c2007-10-05 17:11:30 +0200184 "tftp ${fdt_addr} ${fdt_file};" \
185 "run nfsargs addip addtty;" \
186 "bootm 200000 - ${fdt_addr}\0" \
187 "flash_nfs=run nfsargs addip addtty;" \
188 "bootm ${kernel_addr}\0" \
189 "flash_self=run ramargs addip addtty;" \
190 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
191 "rootpath=/opt/eldk/ppc_4xx\0" \
192 "bootfile=kilauea/uImage\0" \
193 "fdt_file=kilauea/kilauea.dtb\0" \
194 "fdt_addr=400000\0" \
195 "kernel_addr=fc000000\0" \
196 "ramdisk_addr=fc200000\0" \
197 "initrd_high=30000000\0" \
198 "load=tftp 200000 kilauea/u-boot.bin\0" \
199 "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \
200 "cp.b ${fileaddr} fffa0000 ${filesize};" \
201 "setenv filesize;saveenv\0" \
202 "upd=run load update\0" \
203 "nload=tftp 200000 kilauea/u-boot-nand.bin\0" \
204 "nupdate=nand erase 0 60000;nand write 200000 0 60000;" \
205 "setenv filesize;saveenv\0" \
206 "nupd=run nload nupdate\0" \
Stefan Roese566806c2007-10-05 17:11:30 +0200207 "pciconfighost=1\0" \
Stefan Roesed4cb2d12007-10-13 16:43:23 +0200208 "pcie_mode=RP:RP\0" \
Stefan Roese566806c2007-10-05 17:11:30 +0200209 ""
Stefan Roese566806c2007-10-05 17:11:30 +0200210#define CONFIG_BOOTCOMMAND "run flash_self"
211
212#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
213
214#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
215#define CFG_LOADS_BAUD_CHANGE /* allow baudrate change */
216
217/*
218 * BOOTP options
219 */
220#define CONFIG_BOOTP_BOOTFILESIZE
221#define CONFIG_BOOTP_BOOTPATH
222#define CONFIG_BOOTP_GATEWAY
223#define CONFIG_BOOTP_HOSTNAME
224
225/*
226 * Command line configuration.
227 */
228#include <config_cmd_default.h>
229
230#define CONFIG_CMD_ASKENV
231#define CONFIG_CMD_DATE
232#define CONFIG_CMD_DHCP
233#define CONFIG_CMD_DIAG
234#define CONFIG_CMD_DTT
235#define CONFIG_CMD_EEPROM
236#define CONFIG_CMD_ELF
237#define CONFIG_CMD_I2C
238#define CONFIG_CMD_IRQ
239#define CONFIG_CMD_LOG
240#define CONFIG_CMD_MII
241#define CONFIG_CMD_NAND
242#define CONFIG_CMD_NET
243#define CONFIG_CMD_NFS
244#define CONFIG_CMD_PCI
245#define CONFIG_CMD_PING
246#define CONFIG_CMD_REGINFO
247
248/* POST support */
249#define CONFIG_POST (CFG_POST_MEMORY | \
250 CFG_POST_CACHE | \
251 CFG_POST_CPU | \
252 CFG_POST_ETHER | \
253 CFG_POST_I2C | \
254 CFG_POST_MEMORY | \
255 CFG_POST_UART)
256
257/* Define here the base-addresses of the UARTs to test in POST */
258#define CFG_POST_UART_TABLE {UART0_BASE, UART1_BASE}
259
260#define CONFIG_LOGBUFFER
261#define CFG_POST_CACHE_ADDR 0x00800000 /* free virtual address */
262
263#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
264
265#undef CONFIG_WATCHDOG /* watchdog disabled */
266
267/*-----------------------------------------------------------------------
268 * Miscellaneous configurable options
269 *----------------------------------------------------------------------*/
270#define CFG_LONGHELP /* undef to save memory */
271#define CFG_PROMPT "=> " /* Monitor Command Prompt */
272#if defined(CONFIG_CMD_KGDB)
273#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
274#else
275#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
276#endif
277#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
278#define CFG_MAXARGS 16 /* max number of command args */
279#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
280
281#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
282#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
283
284#define CFG_LOAD_ADDR 0x100000 /* default load address */
285#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
286
287#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
288
289#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
290#define CONFIG_LOOPW 1 /* enable loopw command */
291#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
292#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
293#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
294
295/*-----------------------------------------------------------------------
296 * PCI stuff
297 *----------------------------------------------------------------------*/
298#define CONFIG_PCI /* include pci support */
299#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
300#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
301#define CONFIG_PCI_CONFIG_HOST_BRIDGE
302
303/*-----------------------------------------------------------------------
304 * PCIe stuff
305 *----------------------------------------------------------------------*/
306#define CFG_PCIE_MEMBASE 0x90000000 /* mapped PCIe memory */
307#define CFG_PCIE_MEMSIZE 0x08000000 /* 128 Meg, smallest incr per port */
308
309#define CFG_PCIE0_CFGBASE 0xa0000000 /* remote access */
310#define CFG_PCIE0_XCFGBASE 0xb0000000 /* local access */
311#define CFG_PCIE0_CFGMASK 0xe0000001 /* 512 Meg */
312
313#define CFG_PCIE1_CFGBASE 0xc0000000 /* remote access */
314#define CFG_PCIE1_XCFGBASE 0xd0000000 /* local access */
315#define CFG_PCIE1_CFGMASK 0xe0000001 /* 512 Meg */
316
317#define CFG_PCIE0_UTLBASE 0xef502000
318#define CFG_PCIE1_UTLBASE 0xef503000
319
320/* base address of inbound PCIe window */
321#define CFG_PCIE_INBOUND_BASE 0x0000000000000000ULL
322
323/*
324 * For booting Linux, the board info and command line data
325 * have to be in the first 8 MB of memory, since this is
326 * the maximum mapped by the Linux kernel during initialization.
327 */
328#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
329
330/*-----------------------------------------------------------------------
331 * Cache Configuration
332 *----------------------------------------------------------------------*/
333#define CFG_DCACHE_SIZE (16 << 10) /* For IBM 405EX */
334#define CFG_CACHELINE_SIZE 32
335#if defined(CONFIG_CMD_KGDB)
336#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
337#endif
338
339/*-----------------------------------------------------------------------
340 * External Bus Controller (EBC) Setup
341 *----------------------------------------------------------------------*/
342#define CFG_NAND_CS 1 /* NAND chip connected to CSx */
343
344/* Memory Bank 0 (NOR-FLASH) initialization */
345#define CFG_EBC_PB0AP 0x05806500
346#define CFG_EBC_PB0CR 0xFC0DA000 /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/
347
348/* Memory Bank 1 (NAND-FLASH) initialization */
349#define CFG_EBC_PB1AP 0x018003c0
350#define CFG_EBC_PB1CR (CFG_NAND_ADDR | 0x1e000)
351
352/* Memory Bank 2 (FPGA) initialization */
353#define CFG_EBC_PB2AP 0x9400C800
354#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0x800,BS=1MB,BU=R/W,BW=8bit */
355
356#define CFG_EBC_CFG 0x7FC00000 /* EBC0_CFG */
357
358/*-----------------------------------------------------------------------
359 * NAND FLASH
360 *----------------------------------------------------------------------*/
361#define CFG_MAX_NAND_DEVICE 1
362#define NAND_MAX_CHIPS 1
363#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
364#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
365
366/*-----------------------------------------------------------------------
367 * GPIO Setup
368 *----------------------------------------------------------------------*/
369/*-----------------------------------------------------------------------
370 * Definitions for GPIO setup (PPC405EX specific)
371 *
372 * GPIO0[0-3] - EBC data 0-3 inputs/outputs
373 * GPIO0[4-7] - USB data 4-7 inputs/outputs
374 * GPIO0[8-11] - NFCE# 1-3 inputs/outputs, GPIO11: IRQ6 inputs
375 * GPIO0[12-15] - USB data 0-3 inputs/outputs
376 * GPIO0[16-21] - UART0 control signal inputs/outputs
377 *
378 * GPIO0[22-25,27] - EBC control signal inputs/outputs
379 * GPIO0[26] - Instruction trace outputs
380 * GPIO0[28] - Float, N/C
381 * GPIO0[29-31] - DMA control signal inputs/outputs
382 */
383#define CFG_GPIO0_OSRL 0x00AA54AA
384#define CFG_GPIO0_OSRH 0x21800000
385#define CFG_GPIO0_TSRL 0x00AA55AA
386#define CFG_GPIO0_TSRH 0xA5A00000
387
388#define CFG_GPIO0_ISR1L 0x00000100
389#define CFG_GPIO0_ISR1H 0x04000000
390#define CFG_GPIO0_ISR2L 0x00550055
391#define CFG_GPIO0_ISR2H 0x40100000
392
393/*
394 * Internal Definitions
395 *
396 * Boot Flags
397 */
398#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
399#define BOOTFLAG_WARM 0x02 /* Software reboot */
400
401#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
402#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
403#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
404#endif
405
406/*-----------------------------------------------------------------------
407 * Some Kilauea stuff..., mainly fpga registers
408 */
409#define CFG_FPGA_REG_BASE CFG_FPGA_BASE
410#define CFG_FPGA_FIFO_BASE (in32(CFG_FPGA_BASE) | (1 << 11))
411
412/* interrupt */
413#define CFG_FPGA_SLIC0_R_DPRAM_INT 0x80000000
414#define CFG_FPGA_SLIC0_W_DPRAM_INT 0x40000000
415#define CFG_FPGA_SLIC1_R_DPRAM_INT 0x20000000
416#define CFG_FPGA_SLIC1_W_DPRAM_INT 0x10000000
417#define CFG_FPGA_PHY0_INT 0x08000000
418#define CFG_FPGA_PHY1_INT 0x04000000
419#define CFG_FPGA_SLIC0_INT 0x02000000
420#define CFG_FPGA_SLIC1_INT 0x01000000
421
422/* DPRAM setting */
423/* 00: 32B; 01: 64B; 10: 128B; 11: 256B */
424#define CFG_FPGA_DPRAM_R_INT_LINE 0x00400000 /* 64 B */
425#define CFG_FPGA_DPRAM_W_INT_LINE 0x00100000 /* 64 B */
426#define CFG_FPGA_DPRAM_RW_TYPE 0x00080000
427#define CFG_FPGA_DPRAM_RST 0x00040000
428#define CFG_FPGA_UART0_FO 0x00020000
429#define CFG_FPGA_UART1_FO 0x00010000
430
431/* loopback */
432#define CFG_FPGA_CHIPSIDE_LOOPBACK 0x00004000
433#define CFG_FPGA_LINESIDE_LOOPBACK 0x00008000
434#define CFG_FPGA_SLIC0_ENABLE 0x00002000
435#define CFG_FPGA_SLIC1_ENABLE 0x00001000
436#define CFG_FPGA_SLIC0_CS 0x00000800
437#define CFG_FPGA_SLIC1_CS 0x00000400
438#define CFG_FPGA_USER_LED0 0x00000200
439#define CFG_FPGA_USER_LED1 0x00000100
440
441#endif /* __CONFIG_H */
442
Stefan Roese566806c2007-10-05 17:11:30 +0200443/* pass open firmware flat tree */
444#define CONFIG_OF_LIBFDT 1
445#define CONFIG_OF_BOARD_SETUP 1
446
447#define OF_CPU "PowerPC,405EX@0"