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wdenk3d3befa2004-03-14 15:06:13 +00001/*
2 * (C) Copyright 2003, 2004
3 * ARM Ltd.
4 * Philippe Robin, <philippe.robin@arm.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
wdenk3d3befa2004-03-14 15:06:13 +00007 */
8
9/*
wdenk42dfe7a2004-03-14 22:25:36 +000010 * ARM PrimeCell UART's (PL010 & PL011)
wdenk3d3befa2004-03-14 15:06:13 +000011 * ------------------------------------
wdenk42dfe7a2004-03-14 22:25:36 +000012 *
wdenk3d3befa2004-03-14 15:06:13 +000013 * Definitions common to both PL010 & PL011
wdenk42dfe7a2004-03-14 22:25:36 +000014 *
wdenk3d3befa2004-03-14 15:06:13 +000015 */
Rabin Vincent72d5e442010-05-05 09:23:07 +053016
17#ifndef __ASSEMBLY__
18/*
19 * We can use a combined structure for PL010 and PL011, because they overlap
20 * only in common registers.
21 */
22struct pl01x_regs {
23 u32 dr; /* 0x00 Data register */
24 u32 ecr; /* 0x04 Error clear register (Write) */
25 u32 pl010_lcrh; /* 0x08 Line control register, high byte */
26 u32 pl010_lcrm; /* 0x0C Line control register, middle byte */
27 u32 pl010_lcrl; /* 0x10 Line control register, low byte */
28 u32 pl010_cr; /* 0x14 Control register */
29 u32 fr; /* 0x18 Flag register (Read only) */
John Rigby910f1ae2011-04-19 10:42:39 +000030#ifdef CONFIG_PL011_SERIAL_RLCR
31 u32 pl011_rlcr; /* 0x1c Receive line control register */
32#else
Rabin Vincent72d5e442010-05-05 09:23:07 +053033 u32 reserved;
John Rigby910f1ae2011-04-19 10:42:39 +000034#endif
Rabin Vincent72d5e442010-05-05 09:23:07 +053035 u32 ilpr; /* 0x20 IrDA low-power counter register */
36 u32 pl011_ibrd; /* 0x24 Integer baud rate register */
37 u32 pl011_fbrd; /* 0x28 Fractional baud rate register */
38 u32 pl011_lcrh; /* 0x2C Line control register */
39 u32 pl011_cr; /* 0x30 Control register */
40};
Alexander Graf60019852018-01-25 12:05:55 +010041
42#ifdef CONFIG_DM_SERIAL
43
44int pl01x_serial_ofdata_to_platdata(struct udevice *dev);
45int pl01x_serial_probe(struct udevice *dev);
46extern const struct dm_serial_ops pl01x_serial_ops;
47
48struct pl01x_priv {
49 struct pl01x_regs *regs;
50 enum pl01x_type type;
51};
52
53#endif /* CONFIG_DM_SERIAL */
54#endif /* !__ASSEMBLY__ */
wdenk3d3befa2004-03-14 15:06:13 +000055
56#define UART_PL01x_RSR_OE 0x08
57#define UART_PL01x_RSR_BE 0x04
58#define UART_PL01x_RSR_PE 0x02
59#define UART_PL01x_RSR_FE 0x01
60
61#define UART_PL01x_FR_TXFE 0x80
62#define UART_PL01x_FR_RXFF 0x40
63#define UART_PL01x_FR_TXFF 0x20
64#define UART_PL01x_FR_RXFE 0x10
65#define UART_PL01x_FR_BUSY 0x08
66#define UART_PL01x_FR_TMSK (UART_PL01x_FR_TXFF + UART_PL01x_FR_BUSY)
67
wdenk42dfe7a2004-03-14 22:25:36 +000068/*
wdenk3d3befa2004-03-14 15:06:13 +000069 * PL010 definitions
wdenk42dfe7a2004-03-14 22:25:36 +000070 *
wdenk3d3befa2004-03-14 15:06:13 +000071 */
wdenk3d3befa2004-03-14 15:06:13 +000072#define UART_PL010_CR_LPE (1 << 7)
73#define UART_PL010_CR_RTIE (1 << 6)
74#define UART_PL010_CR_TIE (1 << 5)
75#define UART_PL010_CR_RIE (1 << 4)
76#define UART_PL010_CR_MSIE (1 << 3)
77#define UART_PL010_CR_IIRLP (1 << 2)
78#define UART_PL010_CR_SIREN (1 << 1)
79#define UART_PL010_CR_UARTEN (1 << 0)
wdenk42dfe7a2004-03-14 22:25:36 +000080
wdenk3d3befa2004-03-14 15:06:13 +000081#define UART_PL010_LCRH_WLEN_8 (3 << 5)
82#define UART_PL010_LCRH_WLEN_7 (2 << 5)
83#define UART_PL010_LCRH_WLEN_6 (1 << 5)
84#define UART_PL010_LCRH_WLEN_5 (0 << 5)
85#define UART_PL010_LCRH_FEN (1 << 4)
86#define UART_PL010_LCRH_STP2 (1 << 3)
87#define UART_PL010_LCRH_EPS (1 << 2)
88#define UART_PL010_LCRH_PEN (1 << 1)
89#define UART_PL010_LCRH_BRK (1 << 0)
90
91
92#define UART_PL010_BAUD_460800 1
93#define UART_PL010_BAUD_230400 3
94#define UART_PL010_BAUD_115200 7
95#define UART_PL010_BAUD_57600 15
96#define UART_PL010_BAUD_38400 23
97#define UART_PL010_BAUD_19200 47
98#define UART_PL010_BAUD_14400 63
99#define UART_PL010_BAUD_9600 95
100#define UART_PL010_BAUD_4800 191
101#define UART_PL010_BAUD_2400 383
102#define UART_PL010_BAUD_1200 767
wdenk42dfe7a2004-03-14 22:25:36 +0000103/*
wdenk3d3befa2004-03-14 15:06:13 +0000104 * PL011 definitions
wdenk42dfe7a2004-03-14 22:25:36 +0000105 *
wdenk3d3befa2004-03-14 15:06:13 +0000106 */
wdenk3d3befa2004-03-14 15:06:13 +0000107#define UART_PL011_LCRH_SPS (1 << 7)
108#define UART_PL011_LCRH_WLEN_8 (3 << 5)
109#define UART_PL011_LCRH_WLEN_7 (2 << 5)
110#define UART_PL011_LCRH_WLEN_6 (1 << 5)
111#define UART_PL011_LCRH_WLEN_5 (0 << 5)
112#define UART_PL011_LCRH_FEN (1 << 4)
113#define UART_PL011_LCRH_STP2 (1 << 3)
114#define UART_PL011_LCRH_EPS (1 << 2)
115#define UART_PL011_LCRH_PEN (1 << 1)
116#define UART_PL011_LCRH_BRK (1 << 0)
117
118#define UART_PL011_CR_CTSEN (1 << 15)
119#define UART_PL011_CR_RTSEN (1 << 14)
120#define UART_PL011_CR_OUT2 (1 << 13)
121#define UART_PL011_CR_OUT1 (1 << 12)
122#define UART_PL011_CR_RTS (1 << 11)
123#define UART_PL011_CR_DTR (1 << 10)
124#define UART_PL011_CR_RXE (1 << 9)
125#define UART_PL011_CR_TXE (1 << 8)
126#define UART_PL011_CR_LPE (1 << 7)
127#define UART_PL011_CR_IIRLP (1 << 2)
128#define UART_PL011_CR_SIREN (1 << 1)
129#define UART_PL011_CR_UARTEN (1 << 0)
130
131#define UART_PL011_IMSC_OEIM (1 << 10)
132#define UART_PL011_IMSC_BEIM (1 << 9)
133#define UART_PL011_IMSC_PEIM (1 << 8)
134#define UART_PL011_IMSC_FEIM (1 << 7)
135#define UART_PL011_IMSC_RTIM (1 << 6)
136#define UART_PL011_IMSC_TXIM (1 << 5)
137#define UART_PL011_IMSC_RXIM (1 << 4)
138#define UART_PL011_IMSC_DSRMIM (1 << 3)
139#define UART_PL011_IMSC_DCDMIM (1 << 2)
140#define UART_PL011_IMSC_CTSMIM (1 << 1)
141#define UART_PL011_IMSC_RIMIM (1 << 0)