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wdenk4ec3a7f2004-09-28 16:44:41 +00001 /*
2 * Most of this taken from Redboot hal_platform_setup.h with cleanup
3 *
4 * NOTE: I haven't clean this up considerably, just enough to get it
5 * running. See hal_platform_setup.h for the source. See
wdenk400558b2005-04-02 23:52:25 +00006 * board/cradle/lowlevel_init.S for another PXA250 setup that is
wdenk4ec3a7f2004-09-28 16:44:41 +00007 * much cleaner.
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <config.h>
29#include <version.h>
30#include <asm/arch/pxa-regs.h>
31
32DRAM_SIZE: .long CFG_DRAM_SIZE
33
34/* wait for coprocessor write complete */
35 .macro CPWAIT reg
36 mrc p15,0,\reg,c2,c0,0
37 mov \reg,\reg
38 sub pc,pc,#4
39 .endm
40
41
wdenk400558b2005-04-02 23:52:25 +000042.globl lowlevel_init
43lowlevel_init:
wdenk4ec3a7f2004-09-28 16:44:41 +000044
45 mov r10, lr
46
47 /* Set up GPIO pins first ----------------------------------------- */
48
49 ldr r0,=GPSR0
50 ldr r1,=CFG_GPSR0_VAL
51 str r1,[r0]
52
53 ldr r0,=GPSR1
54 ldr r1,=CFG_GPSR1_VAL
55 str r1,[r0]
56
57 ldr r0,=GPSR2
58 ldr r1,=CFG_GPSR2_VAL
59 str r1,[r0]
60
61 ldr r0,=GPCR0
62 ldr r1,=CFG_GPCR0_VAL
63 str r1,[r0]
64
65 ldr r0,=GPCR1
66 ldr r1,=CFG_GPCR1_VAL
67 str r1,[r0]
68
69 ldr r0,=GPCR2
70 ldr r1,=CFG_GPCR2_VAL
71 str r1,[r0]
72
73 ldr r0,=GPDR0
74 ldr r1,=CFG_GPDR0_VAL
75 str r1,[r0]
76
77 ldr r0,=GPDR1
78 ldr r1,=CFG_GPDR1_VAL
79 str r1,[r0]
80
81 ldr r0,=GPDR2
82 ldr r1,=CFG_GPDR2_VAL
83 str r1,[r0]
84
85 ldr r0,=GAFR0_L
86 ldr r1,=CFG_GAFR0_L_VAL
87 str r1,[r0]
88
89 ldr r0,=GAFR0_U
90 ldr r1,=CFG_GAFR0_U_VAL
91 str r1,[r0]
92
93 ldr r0,=GAFR1_L
94 ldr r1,=CFG_GAFR1_L_VAL
95 str r1,[r0]
96
97 ldr r0,=GAFR1_U
98 ldr r1,=CFG_GAFR1_U_VAL
99 str r1,[r0]
100
101 ldr r0,=GAFR2_L
102 ldr r1,=CFG_GAFR2_L_VAL
103 str r1,[r0]
104
105 ldr r0,=GAFR2_U
106 ldr r1,=CFG_GAFR2_U_VAL
107 str r1,[r0]
108
109 ldr r0,=PSSR /* enable GPIO pins */
110 ldr r1,=CFG_PSSR_VAL
111 str r1,[r0]
112
113 /* ---------------------------------------------------------------- */
114 /* Enable memory interface */
115 /* */
116 /* The sequence below is based on the recommended init steps */
117 /* detailed in the Intel PXA250 Operating Systems Developers Guide, */
118 /* Chapter 10. */
119 /* ---------------------------------------------------------------- */
120
121 /* ---------------------------------------------------------------- */
122 /* Step 1: Wait for at least 200 microsedonds to allow internal */
123 /* clocks to settle. Only necessary after hard reset... */
124 /* FIXME: can be optimized later */
125 /* ---------------------------------------------------------------- */
126
127 ldr r3, =OSCR /* reset the OS Timer Count to zero */
128 mov r2, #0
129 str r2, [r3]
130 ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
131 /* so 0x300 should be plenty */
1321:
133 ldr r2, [r3]
134 cmp r4, r2
135 bgt 1b
136
137mem_init:
138
139 ldr r1,=MEMC_BASE /* get memory controller base addr. */
140
141 /* ---------------------------------------------------------------- */
142 /* Step 2a: Initialize Asynchronous static memory controller */
143 /* ---------------------------------------------------------------- */
144
145 /* MSC registers: timing, bus width, mem type */
146
147 /* MSC0: nCS(0,1) */
148 ldr r2,=CFG_MSC0_VAL
149 str r2,[r1, #MSC0_OFFSET]
150 ldr r2,[r1, #MSC0_OFFSET] /* read back to ensure data latches */
151
152 /* MSC1: nCS(2,3) */
153 ldr r2,=CFG_MSC1_VAL
154 str r2,[r1, #MSC1_OFFSET]
155 ldr r2,[r1, #MSC1_OFFSET]
156
157 /* MSC2: nCS(4,5) */
158 ldr r2,=CFG_MSC2_VAL
159 str r2,[r1, #MSC2_OFFSET]
160 ldr r2,[r1, #MSC2_OFFSET]
161
162 /* ---------------------------------------------------------------- */
163 /* Step 2b: Initialize Card Interface */
164 /* ---------------------------------------------------------------- */
165
166 /* MECR: Memory Expansion Card Register */
167 ldr r2,=CFG_MECR_VAL
168 str r2,[r1, #MECR_OFFSET]
169 ldr r2,[r1, #MECR_OFFSET]
170
171 /* MCMEM0: Card Interface slot 0 timing */
172 ldr r2,=CFG_MCMEM0_VAL
173 str r2,[r1, #MCMEM0_OFFSET]
174 ldr r2,[r1, #MCMEM0_OFFSET]
175
176 /* MCMEM1: Card Interface slot 1 timing */
177 ldr r2,=CFG_MCMEM1_VAL
178 str r2,[r1, #MCMEM1_OFFSET]
179 ldr r2,[r1, #MCMEM1_OFFSET]
180
181 /* MCATT0: Card Interface Attribute Space Timing, slot 0 */
182 ldr r2,=CFG_MCATT0_VAL
183 str r2,[r1, #MCATT0_OFFSET]
184 ldr r2,[r1, #MCATT0_OFFSET]
185
186 /* MCATT1: Card Interface Attribute Space Timing, slot 1 */
187 ldr r2,=CFG_MCATT1_VAL
188 str r2,[r1, #MCATT1_OFFSET]
189 ldr r2,[r1, #MCATT1_OFFSET]
190
191 /* MCIO0: Card Interface I/O Space Timing, slot 0 */
192 ldr r2,=CFG_MCIO0_VAL
193 str r2,[r1, #MCIO0_OFFSET]
194 ldr r2,[r1, #MCIO0_OFFSET]
195
196 /* MCIO1: Card Interface I/O Space Timing, slot 1 */
197 ldr r2,=CFG_MCIO1_VAL
198 str r2,[r1, #MCIO1_OFFSET]
199 ldr r2,[r1, #MCIO1_OFFSET]
200
201 /* ---------------------------------------------------------------- */
202 /* Step 2c: Write FLYCNFG FIXME: what's that??? */
203 /* ---------------------------------------------------------------- */
204
205 /* ---------------------------------------------------------------- */
206 /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
207 /* ---------------------------------------------------------------- */
208
209 @ get the mdrefr settings
210 ldr r4,=CFG_MDREFR_VAL
211
212 @ write back mdrefr
213 str r4,[r1, #MDREFR_OFFSET]
214 ldr r4,[r1, #MDREFR_OFFSET]
215
216 /* ---------------------------------------------------------------- */
217 /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
218 /* ---------------------------------------------------------------- */
219
220 /* Initialize SXCNFG register. Assert the enable bits */
221
222 /* Write SXMRS to cause an MRS command to all enabled banks of */
223 /* synchronous static memory. Note that SXLCR need not be written */
224 /* at this time. */
225
226 /* FIXME: we use async mode for now */
227
228 /* ---------------------------------------------------------------- */
229 /* Step 4: Initialize SDRAM */
230 /* ---------------------------------------------------------------- */
231
232 @ set K1RUN for bank 0
233 @
234 orr r4, r4, #MDREFR_K1RUN
235
236 @ write back mdrefr
237 @
238 str r4, [r1, #MDREFR_OFFSET]
239 ldr r4, [r1, #MDREFR_OFFSET]
240
241 @ deassert SLFRSH
242 @
243 bic r4, r4, #MDREFR_SLFRSH
244
245 @ write back mdrefr
246 @
247 str r4, [r1, #MDREFR_OFFSET]
248 ldr r4, [r1, #MDREFR_OFFSET]
249
250 @ assert E1PIN
251 @ if E0PIN is also used: #(MDREFR_E1PIN|MDREFR_E0PIN)
252 orr r4, r4, #(MDREFR_E1PIN)
253
254 @ write back mdrefr
255 @
256 str r4, [r1, #MDREFR_OFFSET]
257 ldr r4, [r1, #MDREFR_OFFSET]
258 nop
259 nop
260
261 /* Step 4d: */
262 /* fetch platform value of mdcnfg */
263 @
264 ldr r2, =CFG_MDCNFG_VAL
265
266 @ disable all sdram banks
267 @
268 bic r2, r2, #(MDCNFG_DE0 | MDCNFG_DE1)
269 bic r2, r2, #(MDCNFG_DE2 | MDCNFG_DE3)
270
271 @ program banks 0/1 for bus width
272 @
273 bic r2, r2, #MDCNFG_DWID0 @0=32-bit
274
275 @ write initial value of mdcnfg, w/o enabling sdram banks
276 @
277 str r2, [r1, #MDCNFG_OFFSET]
278
279 /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
280 /* 100..200 µsec. */
281
282 ldr r3, =OSCR /* reset the OS Timer Count to zero */
283 mov r2, #0
284 str r2, [r3]
285 ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
286 /* so 0x300 should be plenty */
2871:
288 ldr r2, [r3]
289 cmp r4, r2
290 bgt 1b
291
292
293 /* Step 4f: Trigger a number (usually 8) refresh cycles by */
294 /* attempting non-burst read or write accesses to disabled */
295 /* SDRAM, as commonly specified in the power up sequence */
296 /* documented in SDRAM data sheets. The address(es) used */
297 /* for this purpose must not be cacheable. */
298
299 ldr r3, =CFG_DRAM_BASE
300 str r2, [r3]
301 str r2, [r3]
302 str r2, [r3]
303 str r2, [r3]
304 str r2, [r3]
305 str r2, [r3]
306 str r2, [r3]
307 str r2, [r3]
308 str r2, [r3]
309
310
311 /* Step 4g: Write MDCNFG with enable bits asserted */
312 /* get memory controller base address */
313 ldr r1, =MEMC_BASE
314
315 @fetch current mdcnfg value
316 @
317 ldr r3, [r1, #MDCNFG_OFFSET]
318
319 @enable sdram bank 0 if installed (must do for any populated bank)
320 @
321 orr r3, r3, #MDCNFG_DE0
322
323 @write back mdcnfg, enabling the sdram bank(s)
324 @
325 str r3, [r1, #MDCNFG_OFFSET]
326
327 /* Step 4h: Write MDMRS. */
328
329 ldr r2, =CFG_MDMRS_VAL
330 str r2, [r1, #MDMRS_OFFSET]
331
332
333 /* We are finished with Intel's memory controller initialisation */
334
335
336 /* ---------------------------------------------------------------- */
337 /* Disable (mask) all interrupts at interrupt controller */
338 /* ---------------------------------------------------------------- */
339
340initirqs:
341 mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
342 ldr r2, =ICLR
343 str r1, [r2]
344
345 ldr r1, =CFG_ICMR_VAL /* mask all interrupts at the controller */
346 ldr r2, =ICMR
347 str r1, [r2]
348
349
350 /* ---------------------------------------------------------------- */
351 /* Clock initialisation */
352 /* ---------------------------------------------------------------- */
353
354initclks:
355
356 /* Disable the peripheral clocks, and set the core clock frequency */
357 /* (hard-coding at 398.12MHz for now). */
358 /* Turn Off ALL on-chip peripheral clocks for re-configuration */
359 /* Note: See label 'ENABLECLKS' for the re-enabling */
360 ldr r1, =CKEN
361 mov r2, #0
362 str r2, [r1]
363
364
365 /* default value */
366 ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
367
368 /* ... and write the core clock config register */
369 ldr r1, =CCCR
370 str r2, [r1]
371
372#ifdef RTC
373 /* enable the 32Khz oscillator for RTC and PowerManager */
374
375 ldr r1, =OSCC
376 mov r2, #OSCC_OON
377 str r2, [r1]
378
379 /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
380 /* has settled. */
38160:
382 ldr r2, [r1]
383 ands r2, r2, #1
384 beq 60b
385#endif
386
387 @ Turn on needed clocks
388 @
389test:
390 ldr r1, =CKEN
391 ldr r2, =CFG_CKEN_VAL
392 str r2, [r1]
393
394 /* ---------------------------------------------------------------- */
395 /* */
396 /* ---------------------------------------------------------------- */
397
398 /* Save SDRAM size ?*/
399 ldr r1, =DRAM_SIZE
400 str r8, [r1]
401
402 /* FIXME */
403
404#define NODEBUG
405#ifdef NODEBUG
406 /*Disable software and data breakpoints */
407 mov r0,#0
408 mcr p15,0,r0,c14,c8,0 /* ibcr0 */
409 mcr p15,0,r0,c14,c9,0 /* ibcr1 */
410 mcr p15,0,r0,c14,c4,0 /* dbcon */
411
412 /*Enable all debug functionality */
413 mov r0,#0x80000000
414 mcr p14,0,r0,c10,c0,0 /* dcsr */
415
416#endif
417
418 /* ---------------------------------------------------------------- */
wdenk400558b2005-04-02 23:52:25 +0000419 /* End lowlevel_init */
wdenk4ec3a7f2004-09-28 16:44:41 +0000420 /* ---------------------------------------------------------------- */
421
wdenk400558b2005-04-02 23:52:25 +0000422endlowlevel_init:
wdenk4ec3a7f2004-09-28 16:44:41 +0000423
424 mov pc, lr