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Mike Frysinger76d21802008-10-12 05:05:42 -04001/*
2 * video.c - run splash screen on lcd
3 *
4 * Copyright (c) 2007-2008 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#include <stdarg.h>
10#include <common.h>
11#include <config.h>
12#include <malloc.h>
13#include <asm/blackfin.h>
Mike Frysingerd1f49b42010-06-02 19:29:47 -040014#include <asm/gpio.h>
15#include <asm/portmux.h>
Mike Frysinger76d21802008-10-12 05:05:42 -040016#include <asm/mach-common/bits/dma.h>
17#include <i2c.h>
18#include <linux/types.h>
Jean-Christophe PLAGNIOL-VILLARD52cb4d42009-05-16 12:14:54 +020019#include <stdio_dev.h>
Mike Frysinger76d21802008-10-12 05:05:42 -040020
Mike Frysinger42c6e9a2012-02-03 20:44:54 -050021#include <lzma/LzmaTypes.h>
22#include <lzma/LzmaDec.h>
23#include <lzma/LzmaTools.h>
24
Mike Frysinger76d21802008-10-12 05:05:42 -040025#define DMA_SIZE16 2
26
27#include <asm/mach-common/bits/eppi.h>
28
Mike Frysinger42c6e9a2012-02-03 20:44:54 -050029#include EASYLOGO_HEADER
Mike Frysinger76d21802008-10-12 05:05:42 -040030
31#define LCD_X_RES 480 /*Horizontal Resolution */
32#define LCD_Y_RES 272 /* Vertical Resolution */
33
34#define LCD_BPP 24 /* Bit Per Pixel */
35#define LCD_PIXEL_SIZE (LCD_BPP / 8)
36#define DMA_BUS_SIZE 32
37#define ACTIVE_VIDEO_MEM_OFFSET 0
38
39/* -- Horizontal synchronizing --
40 *
41 * Timing characteristics taken from the SHARP LQ043T1DG01 datasheet
42 * (LCY-W-06602A Page 9 of 22)
43 *
44 * Clock Frequency 1/Tc Min 7.83 Typ 9.00 Max 9.26 MHz
45 *
46 * Period TH - 525 - Clock
47 * Pulse width THp - 41 - Clock
48 * Horizontal period THd - 480 - Clock
49 * Back porch THb - 2 - Clock
50 * Front porch THf - 2 - Clock
51 *
52 * -- Vertical synchronizing --
53 * Period TV - 286 - Line
54 * Pulse width TVp - 10 - Line
55 * Vertical period TVd - 272 - Line
56 * Back porch TVb - 2 - Line
57 * Front porch TVf - 2 - Line
58 */
59
60#define LCD_CLK (8*1000*1000) /* 8MHz */
61
62/* # active data to transfer after Horizontal Delay clock */
63#define EPPI_HCOUNT LCD_X_RES
64
65/* # active lines to transfer after Vertical Delay clock */
66#define EPPI_VCOUNT LCD_Y_RES
67
68/* Samples per Line = 480 (active data) + 45 (padding) */
69#define EPPI_LINE 525
70
71/* Lines per Frame = 272 (active data) + 14 (padding) */
72#define EPPI_FRAME 286
73
74/* FS1 (Hsync) Width (Typical)*/
75#define EPPI_FS1W_HBL 41
76
77/* FS1 (Hsync) Period (Typical) */
78#define EPPI_FS1P_AVPL EPPI_LINE
79
80/* Horizontal Delay clock after assertion of Hsync (Typical) */
81#define EPPI_HDELAY 43
82
83/* FS2 (Vsync) Width = FS1 (Hsync) Period * 10 */
84#define EPPI_FS2W_LVB (EPPI_LINE * 10)
85
86 /* FS2 (Vsync) Period = FS1 (Hsync) Period * Lines per Frame */
87#define EPPI_FS2P_LAVF (EPPI_LINE * EPPI_FRAME)
88
89/* Vertical Delay after assertion of Vsync (2 Lines) */
90#define EPPI_VDELAY 12
91
92#define EPPI_CLIP 0xFF00FF00
93
94/* EPPI Control register configuration value for RGB out
95 * - EPPI as Output
96 * GP 2 frame sync mode,
97 * Internal Clock generation disabled, Internal FS generation enabled,
98 * Receives samples on EPPI_CLK raising edge, Transmits samples on EPPI_CLK falling edge,
99 * FS1 & FS2 are active high,
100 * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out)
101 * DMA Unpacking disabled when RGB Formating is enabled, otherwise DMA unpacking enabled
102 * Swapping Enabled,
103 * One (DMA) Channel Mode,
104 * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output
105 * Regular watermark - when FIFO is 100% full,
106 * Urgent watermark - when FIFO is 75% full
107 */
108
109#define EPPI_CONTROL (0x20136E2E)
110
111static inline u16 get_eppi_clkdiv(u32 target_ppi_clk)
112{
113 u32 sclk = get_sclk();
114
115 /* EPPI_CLK = (SCLK) / (2 * (EPPI_CLKDIV[15:0] + 1)) */
116
117 return (((sclk / target_ppi_clk) / 2) - 1);
118}
119
120void Init_PPI(void)
121{
122 u16 eppi_clkdiv = get_eppi_clkdiv(LCD_CLK);
123
124 bfin_write_EPPI0_FS1W_HBL(EPPI_FS1W_HBL);
125 bfin_write_EPPI0_FS1P_AVPL(EPPI_FS1P_AVPL);
126 bfin_write_EPPI0_FS2W_LVB(EPPI_FS2W_LVB);
127 bfin_write_EPPI0_FS2P_LAVF(EPPI_FS2P_LAVF);
128 bfin_write_EPPI0_CLIP(EPPI_CLIP);
129
130 bfin_write_EPPI0_FRAME(EPPI_FRAME);
131 bfin_write_EPPI0_LINE(EPPI_LINE);
132
133 bfin_write_EPPI0_HCOUNT(EPPI_HCOUNT);
134 bfin_write_EPPI0_HDELAY(EPPI_HDELAY);
135 bfin_write_EPPI0_VCOUNT(EPPI_VCOUNT);
136 bfin_write_EPPI0_VDELAY(EPPI_VDELAY);
137
138 bfin_write_EPPI0_CLKDIV(eppi_clkdiv);
139
140/*
141 * DLEN = 6 (24 bits for RGB888 out) or 5 (18 bits for RGB666 out)
142 * RGB Formatting Enabled for RGB666 output, disabled for RGB888 output
143 */
144#if defined(CONFIG_VIDEO_RGB666)
145 bfin_write_EPPI0_CONTROL((EPPI_CONTROL & ~DLENGTH) | DLEN_18 |
146 RGB_FMT_EN);
147#else
148 bfin_write_EPPI0_CONTROL(((EPPI_CONTROL & ~DLENGTH) | DLEN_24) &
149 ~RGB_FMT_EN);
150#endif
151
152}
153
154#define DEB2_URGENT 0x2000 /* DEB2 Urgent */
155
156void Init_DMA(void *dst)
157{
158
159#if defined(CONFIG_DEB_DMA_URGENT)
Mike Frysingerbf0a29c2010-07-25 17:19:00 -0400160 bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | DEB2_URGENT);
Mike Frysinger76d21802008-10-12 05:05:42 -0400161#endif
162
Mike Frysingerbf0a29c2010-07-25 17:19:00 -0400163 bfin_write_DMA12_START_ADDR(dst);
Mike Frysinger76d21802008-10-12 05:05:42 -0400164
165 /* X count */
Mike Frysingerbf0a29c2010-07-25 17:19:00 -0400166 bfin_write_DMA12_X_COUNT((LCD_X_RES * LCD_BPP) / DMA_BUS_SIZE);
167 bfin_write_DMA12_X_MODIFY(DMA_BUS_SIZE / 8);
Mike Frysinger76d21802008-10-12 05:05:42 -0400168
169 /* Y count */
Mike Frysingerbf0a29c2010-07-25 17:19:00 -0400170 bfin_write_DMA12_Y_COUNT(LCD_Y_RES);
171 bfin_write_DMA12_Y_MODIFY(DMA_BUS_SIZE / 8);
Mike Frysinger76d21802008-10-12 05:05:42 -0400172
173 /* DMA Config */
Mike Frysingerbf0a29c2010-07-25 17:19:00 -0400174 bfin_write_DMA12_CONFIG(
Mike Frysinger76d21802008-10-12 05:05:42 -0400175 WDSIZE_32 | /* 32 bit DMA */
176 DMA2D | /* 2D DMA */
Mike Frysingerbf0a29c2010-07-25 17:19:00 -0400177 FLOW_AUTO /* autobuffer mode */
178 );
Mike Frysinger76d21802008-10-12 05:05:42 -0400179}
180
181void Init_Ports(void)
182{
Mike Frysingerd1f49b42010-06-02 19:29:47 -0400183 const unsigned short pins[] = {
184 P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, P_PPI0_D4,
185 P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, P_PPI0_D8, P_PPI0_D9,
186 P_PPI0_D10, P_PPI0_D11, P_PPI0_D12, P_PPI0_D13, P_PPI0_D14,
187 P_PPI0_D15, P_PPI0_D16, P_PPI0_D17,
Mike Frysinger76d21802008-10-12 05:05:42 -0400188#if !defined(CONFIG_VIDEO_RGB666)
Mike Frysingerd1f49b42010-06-02 19:29:47 -0400189 P_PPI0_D18, P_PPI0_D19, P_PPI0_D20, P_PPI0_D21, P_PPI0_D22,
190 P_PPI0_D23,
Mike Frysinger76d21802008-10-12 05:05:42 -0400191#endif
Mike Frysingerd1f49b42010-06-02 19:29:47 -0400192 P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, 0,
193 };
194 peripheral_request_list(pins, "lcd");
Mike Frysinger76d21802008-10-12 05:05:42 -0400195
Mike Frysingerd1f49b42010-06-02 19:29:47 -0400196 gpio_request(GPIO_PE3, "lcd-disp");
197 gpio_direction_output(GPIO_PE3, 1);
Mike Frysinger76d21802008-10-12 05:05:42 -0400198}
199
200void EnableDMA(void)
201{
Mike Frysingerbf0a29c2010-07-25 17:19:00 -0400202 bfin_write_DMA12_CONFIG(bfin_read_DMA12_CONFIG() | DMAEN);
Mike Frysinger76d21802008-10-12 05:05:42 -0400203}
204
205void DisableDMA(void)
206{
Mike Frysingerbf0a29c2010-07-25 17:19:00 -0400207 bfin_write_DMA12_CONFIG(bfin_read_DMA12_CONFIG() & ~DMAEN);
Mike Frysinger76d21802008-10-12 05:05:42 -0400208}
209
210/* enable and disable PPI functions */
211void EnablePPI(void)
212{
213 bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() | EPPI_EN);
214}
215
216void DisablePPI(void)
217{
218 bfin_write_EPPI0_CONTROL(bfin_read_EPPI0_CONTROL() & ~EPPI_EN);
219}
220
221int video_init(void *dst)
222{
223 Init_Ports();
224 Init_DMA(dst);
225 EnableDMA();
226 Init_PPI();
227 EnablePPI();
228
229 return 0;
230}
231
Michael Hennerich5fc564e2009-08-07 02:47:54 +0000232void video_stop(void)
233{
234 DisablePPI();
235 DisableDMA();
236}
237
Mike Frysinger76d21802008-10-12 05:05:42 -0400238static void dma_bitblit(void *dst, fastimage_t *logo, int x, int y)
239{
240 if (dcache_status())
241 blackfin_dcache_flush_range(logo->data, logo->data + logo->size);
242
243 bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
244
245 /* Setup destination start address */
246 bfin_write_MDMA_D0_START_ADDR(dst + ((x & -2) * LCD_PIXEL_SIZE)
247 + (y * LCD_X_RES * LCD_PIXEL_SIZE));
248 /* Setup destination xcount */
249 bfin_write_MDMA_D0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
250 /* Setup destination xmodify */
251 bfin_write_MDMA_D0_X_MODIFY(DMA_SIZE16);
252
253 /* Setup destination ycount */
254 bfin_write_MDMA_D0_Y_COUNT(logo->height);
255 /* Setup destination ymodify */
256 bfin_write_MDMA_D0_Y_MODIFY((LCD_X_RES - logo->width) * LCD_PIXEL_SIZE + DMA_SIZE16);
257
258
259 /* Setup Source start address */
260 bfin_write_MDMA_S0_START_ADDR(logo->data);
261 /* Setup Source xcount */
262 bfin_write_MDMA_S0_X_COUNT(logo->width * LCD_PIXEL_SIZE / DMA_SIZE16);
263 /* Setup Source xmodify */
264 bfin_write_MDMA_S0_X_MODIFY(DMA_SIZE16);
265
266 /* Setup Source ycount */
267 bfin_write_MDMA_S0_Y_COUNT(logo->height);
268 /* Setup Source ymodify */
269 bfin_write_MDMA_S0_Y_MODIFY(DMA_SIZE16);
270
271
272 /* Enable source DMA */
273 bfin_write_MDMA_S0_CONFIG(DMAEN | WDSIZE_16 | DMA2D);
274 SSYNC();
275 bfin_write_MDMA_D0_CONFIG(WNR | DMAEN | WDSIZE_16 | DMA2D);
276
277 while (bfin_read_MDMA_D0_IRQ_STATUS() & DMA_RUN);
278
279 bfin_write_MDMA_S0_IRQ_STATUS(bfin_read_MDMA_S0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
280 bfin_write_MDMA_D0_IRQ_STATUS(bfin_read_MDMA_D0_IRQ_STATUS() | DMA_DONE | DMA_ERR);
281
282}
283
Mike Frysinger76d21802008-10-12 05:05:42 -0400284int drv_video_init(void)
285{
286 int error, devices = 1;
Jean-Christophe PLAGNIOL-VILLARD52cb4d42009-05-16 12:14:54 +0200287 struct stdio_dev videodev;
Mike Frysinger76d21802008-10-12 05:05:42 -0400288
289 u8 *dst;
290 u32 fbmem_size = LCD_X_RES * LCD_Y_RES * LCD_PIXEL_SIZE + ACTIVE_VIDEO_MEM_OFFSET;
291
292 dst = malloc(fbmem_size);
293
294 if (dst == NULL) {
295 printf("Failed to alloc FB memory\n");
296 return -1;
297 }
298
299#ifdef EASYLOGO_ENABLE_GZIP
300 unsigned char *data = EASYLOGO_DECOMP_BUFFER;
301 unsigned long src_len = EASYLOGO_ENABLE_GZIP;
Mike Frysinger42c6e9a2012-02-03 20:44:54 -0500302 error = gunzip(data, bfin_logo.size, bfin_logo.data, &src_len);
303 bfin_logo.data = data;
304#elif defined(EASYLOGO_ENABLE_LZMA)
305 unsigned char *data = EASYLOGO_DECOMP_BUFFER;
306 SizeT lzma_len = bfin_logo.size;
307 error = lzmaBuffToBuffDecompress(data, &lzma_len,
308 bfin_logo.data, EASYLOGO_ENABLE_LZMA);
309 bfin_logo.data = data;
310#else
311 error = 0;
312#endif
313
314 if (error) {
Mike Frysinger76d21802008-10-12 05:05:42 -0400315 puts("Failed to decompress logo\n");
316 free(dst);
317 return -1;
318 }
Mike Frysinger76d21802008-10-12 05:05:42 -0400319
320 memset(dst + ACTIVE_VIDEO_MEM_OFFSET, bfin_logo.data[0], fbmem_size - ACTIVE_VIDEO_MEM_OFFSET);
321
322 dma_bitblit(dst + ACTIVE_VIDEO_MEM_OFFSET, &bfin_logo,
323 (LCD_X_RES - bfin_logo.width) / 2,
324 (LCD_Y_RES - bfin_logo.height) / 2);
325
326 video_init(dst); /* Video initialization */
327
328 memset(&videodev, 0, sizeof(videodev));
329
330 strcpy(videodev.name, "video");
Mike Frysinger76d21802008-10-12 05:05:42 -0400331
Jean-Christophe PLAGNIOL-VILLARD52cb4d42009-05-16 12:14:54 +0200332 error = stdio_register(&videodev);
Mike Frysinger76d21802008-10-12 05:05:42 -0400333
334 return (error == 0) ? devices : error;
335}