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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / d4f0ff93c8a7ef743eeea38f9782aad7bcd6fcf5 / . / arch / arm / dts / t8103-pmgr.dtsi
blob: 82ea4aa322e04d0362ebdb263e1a790dcaf78908 [file] [log] [blame]
Mark Kettenisc918e2c2022-01-10 20:58:42 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2/*
3 * PMGR Power domains for the Apple T8103 "M1" SoC
4 *
5 * Copyright The Asahi Linux Contributors
6 */
7
8
9&pmgr {
10 ps_sbr: power-controller@100 {
11 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
12 reg = <0x100 4>;
13 #power-domain-cells = <0>;
14 #reset-cells = <0>;
15 label = "sbr";
16 apple,always-on; /* Core device */
17 };
18
19 ps_aic: power-controller@108 {
20 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
21 reg = <0x108 4>;
22 #power-domain-cells = <0>;
23 #reset-cells = <0>;
24 label = "aic";
25 apple,always-on; /* Core device */
26 };
27
28 ps_dwi: power-controller@110 {
29 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
30 reg = <0x110 4>;
31 #power-domain-cells = <0>;
32 #reset-cells = <0>;
33 label = "dwi";
34 apple,always-on; /* Core device */
35 };
36
37 ps_soc_spmi0: power-controller@118 {
38 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
39 reg = <0x118 4>;
40 #power-domain-cells = <0>;
41 #reset-cells = <0>;
42 label = "soc_spmi0";
43 };
44
45 ps_soc_spmi1: power-controller@120 {
46 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
47 reg = <0x120 4>;
48 #power-domain-cells = <0>;
49 #reset-cells = <0>;
50 label = "soc_spmi1";
51 };
52
53 ps_soc_spmi2: power-controller@128 {
54 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
55 reg = <0x128 4>;
56 #power-domain-cells = <0>;
57 #reset-cells = <0>;
58 label = "soc_spmi2";
59 };
60
61 ps_gpio: power-controller@130 {
62 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
63 reg = <0x130 4>;
64 #power-domain-cells = <0>;
65 #reset-cells = <0>;
66 label = "gpio";
67 };
68
69 ps_pms_busif: power-controller@138 {
70 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
71 reg = <0x138 4>;
72 #power-domain-cells = <0>;
73 #reset-cells = <0>;
74 label = "pms_busif";
75 apple,always-on; /* Core device */
76 };
77
78 ps_pms: power-controller@140 {
79 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
80 reg = <0x140 4>;
81 #power-domain-cells = <0>;
82 #reset-cells = <0>;
83 label = "pms";
84 apple,always-on; /* Core device */
85 };
86
87 ps_pms_fpwm0: power-controller@148 {
88 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
89 reg = <0x148 4>;
90 #power-domain-cells = <0>;
91 #reset-cells = <0>;
92 label = "pms_fpwm0";
93 power-domains = <&ps_pms>;
94 };
95
96 ps_pms_fpwm1: power-controller@150 {
97 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
98 reg = <0x150 4>;
99 #power-domain-cells = <0>;
100 #reset-cells = <0>;
101 label = "pms_fpwm1";
102 power-domains = <&ps_pms>;
103 };
104
105 ps_pms_fpwm2: power-controller@158 {
106 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
107 reg = <0x158 4>;
108 #power-domain-cells = <0>;
109 #reset-cells = <0>;
110 label = "pms_fpwm2";
111 power-domains = <&ps_pms>;
112 };
113
114 ps_pms_fpwm3: power-controller@160 {
115 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
116 reg = <0x160 4>;
117 #power-domain-cells = <0>;
118 #reset-cells = <0>;
119 label = "pms_fpwm3";
120 power-domains = <&ps_pms>;
121 };
122
123 ps_pms_fpwm4: power-controller@168 {
124 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
125 reg = <0x168 4>;
126 #power-domain-cells = <0>;
127 #reset-cells = <0>;
128 label = "pms_fpwm4";
129 power-domains = <&ps_pms>;
130 };
131
132 ps_soc_dpe: power-controller@170 {
133 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
134 reg = <0x170 4>;
135 #power-domain-cells = <0>;
136 #reset-cells = <0>;
137 label = "soc_dpe";
138 apple,always-on; /* Core device */
139 };
140
141 ps_pmgr_soc_ocla: power-controller@178 {
142 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
143 reg = <0x178 4>;
144 #power-domain-cells = <0>;
145 #reset-cells = <0>;
146 label = "pmgr_soc_ocla";
147 };
148
149 ps_ispsens0: power-controller@180 {
150 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
151 reg = <0x180 4>;
152 #power-domain-cells = <0>;
153 #reset-cells = <0>;
154 label = "ispsens0";
155 };
156
157 ps_ispsens1: power-controller@188 {
158 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
159 reg = <0x188 4>;
160 #power-domain-cells = <0>;
161 #reset-cells = <0>;
162 label = "ispsens1";
163 };
164
165 ps_ispsens2: power-controller@190 {
166 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
167 reg = <0x190 4>;
168 #power-domain-cells = <0>;
169 #reset-cells = <0>;
170 label = "ispsens2";
171 };
172
173 ps_ispsens3: power-controller@198 {
174 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
175 reg = <0x198 4>;
176 #power-domain-cells = <0>;
177 #reset-cells = <0>;
178 label = "ispsens3";
179 };
180
181 ps_pcie_ref: power-controller@1a0 {
182 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
183 reg = <0x1a0 4>;
184 #power-domain-cells = <0>;
185 #reset-cells = <0>;
186 label = "pcie_ref";
187 };
188
189 ps_aft0: power-controller@1a8 {
190 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
191 reg = <0x1a8 4>;
192 #power-domain-cells = <0>;
193 #reset-cells = <0>;
194 label = "aft0";
195 };
196
197 ps_devc0_ivdmc: power-controller@1b0 {
198 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
199 reg = <0x1b0 4>;
200 #power-domain-cells = <0>;
201 #reset-cells = <0>;
202 label = "devc0_ivdmc";
203 };
204
205 ps_imx: power-controller@1b8 {
206 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
207 reg = <0x1b8 4>;
208 #power-domain-cells = <0>;
209 #reset-cells = <0>;
210 label = "imx";
211 apple,always-on; /* Apple fabric, critical block */
212 };
213
214 ps_sio_busif: power-controller@1c0 {
215 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
216 reg = <0x1c0 4>;
217 #power-domain-cells = <0>;
218 #reset-cells = <0>;
219 label = "sio_busif";
220 };
221
222 ps_sio: power-controller@1c8 {
223 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
224 reg = <0x1c8 4>;
225 #power-domain-cells = <0>;
226 #reset-cells = <0>;
227 label = "sio";
228 power-domains = <&ps_sio_busif>;
229 };
230
231 ps_sio_cpu: power-controller@1d0 {
232 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
233 reg = <0x1d0 4>;
234 #power-domain-cells = <0>;
235 #reset-cells = <0>;
236 label = "sio_cpu";
237 power-domains = <&ps_sio>;
238 };
239
240 ps_fpwm0: power-controller@1d8 {
241 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
242 reg = <0x1d8 4>;
243 #power-domain-cells = <0>;
244 #reset-cells = <0>;
245 label = "fpwm0";
246 };
247
248 ps_fpwm1: power-controller@1e0 {
249 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
250 reg = <0x1e0 4>;
251 #power-domain-cells = <0>;
252 #reset-cells = <0>;
253 label = "fpwm1";
254 };
255
256 ps_fpwm2: power-controller@1e8 {
257 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
258 reg = <0x1e8 4>;
259 #power-domain-cells = <0>;
260 #reset-cells = <0>;
261 label = "fpwm2";
262 };
263
264 ps_i2c0: power-controller@1f0 {
265 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
266 reg = <0x1f0 4>;
267 #power-domain-cells = <0>;
268 #reset-cells = <0>;
269 label = "i2c0";
270 power-domains = <&ps_sio>;
271 };
272
273 ps_i2c1: power-controller@1f8 {
274 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
275 reg = <0x1f8 4>;
276 #power-domain-cells = <0>;
277 #reset-cells = <0>;
278 label = "i2c1";
279 power-domains = <&ps_sio>;
280 };
281
282 ps_i2c2: power-controller@200 {
283 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
284 reg = <0x200 4>;
285 #power-domain-cells = <0>;
286 #reset-cells = <0>;
287 label = "i2c2";
288 power-domains = <&ps_sio>;
289 };
290
291 ps_i2c3: power-controller@208 {
292 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
293 reg = <0x208 4>;
294 #power-domain-cells = <0>;
295 #reset-cells = <0>;
296 label = "i2c3";
297 power-domains = <&ps_sio>;
298 };
299
300 ps_i2c4: power-controller@210 {
301 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
302 reg = <0x210 4>;
303 #power-domain-cells = <0>;
304 #reset-cells = <0>;
305 label = "i2c4";
306 power-domains = <&ps_sio>;
307 };
308
309 ps_spi_p: power-controller@218 {
310 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
311 reg = <0x218 4>;
312 #power-domain-cells = <0>;
313 #reset-cells = <0>;
314 label = "spi_p";
315 power-domains = <&ps_sio>;
316 };
317
318 ps_uart_p: power-controller@220 {
319 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
320 reg = <0x220 4>;
321 #power-domain-cells = <0>;
322 #reset-cells = <0>;
323 label = "uart_p";
324 power-domains = <&ps_sio>;
325 };
326
327 ps_audio_p: power-controller@228 {
328 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
329 reg = <0x228 4>;
330 #power-domain-cells = <0>;
331 #reset-cells = <0>;
332 label = "audio_p";
333 power-domains = <&ps_sio>;
334 };
335
336 ps_sio_adma: power-controller@230 {
337 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
338 reg = <0x230 4>;
339 #power-domain-cells = <0>;
340 #reset-cells = <0>;
341 label = "sio_adma";
342 power-domains = <&ps_sio>, <&ps_pms>;
343 };
344
345 ps_aes: power-controller@238 {
346 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
347 reg = <0x238 4>;
348 #power-domain-cells = <0>;
349 #reset-cells = <0>;
350 label = "aes";
351 power-domains = <&ps_sio>;
352 };
353
354 ps_spi0: power-controller@240 {
355 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
356 reg = <0x240 4>;
357 #power-domain-cells = <0>;
358 #reset-cells = <0>;
359 label = "spi0";
360 power-domains = <&ps_sio>, <&ps_spi_p>;
361 };
362
363 ps_spi1: power-controller@248 {
364 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
365 reg = <0x248 4>;
366 #power-domain-cells = <0>;
367 #reset-cells = <0>;
368 label = "spi1";
369 power-domains = <&ps_sio>, <&ps_spi_p>;
370 };
371
372 ps_spi2: power-controller@250 {
373 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
374 reg = <0x250 4>;
375 #power-domain-cells = <0>;
376 #reset-cells = <0>;
377 label = "spi2";
378 power-domains = <&ps_sio>, <&ps_spi_p>;
379 };
380
381 ps_spi3: power-controller@258 {
382 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
383 reg = <0x258 4>;
384 #power-domain-cells = <0>;
385 #reset-cells = <0>;
386 label = "spi3";
387 power-domains = <&ps_sio>, <&ps_spi_p>;
388 };
389
390 ps_uart_n: power-controller@268 {
391 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
392 reg = <0x268 4>;
393 #power-domain-cells = <0>;
394 #reset-cells = <0>;
395 label = "uart_n";
396 power-domains = <&ps_uart_p>;
397 };
398
399 ps_uart0: power-controller@270 {
400 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
401 reg = <0x270 4>;
402 #power-domain-cells = <0>;
403 #reset-cells = <0>;
404 label = "uart0";
405 power-domains = <&ps_uart_p>;
406 };
407
408 ps_uart1: power-controller@278 {
409 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
410 reg = <0x278 4>;
411 #power-domain-cells = <0>;
412 #reset-cells = <0>;
413 label = "uart1";
414 power-domains = <&ps_uart_p>;
415 };
416
417 ps_uart2: power-controller@280 {
418 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
419 reg = <0x280 4>;
420 #power-domain-cells = <0>;
421 #reset-cells = <0>;
422 label = "uart2";
423 power-domains = <&ps_uart_p>;
424 };
425
426 ps_uart3: power-controller@288 {
427 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
428 reg = <0x288 4>;
429 #power-domain-cells = <0>;
430 #reset-cells = <0>;
431 label = "uart3";
432 power-domains = <&ps_uart_p>;
433 };
434
435 ps_uart4: power-controller@290 {
436 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
437 reg = <0x290 4>;
438 #power-domain-cells = <0>;
439 #reset-cells = <0>;
440 label = "uart4";
441 power-domains = <&ps_uart_p>;
442 };
443
444 ps_uart5: power-controller@298 {
445 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
446 reg = <0x298 4>;
447 #power-domain-cells = <0>;
448 #reset-cells = <0>;
449 label = "uart5";
450 power-domains = <&ps_uart_p>;
451 };
452
453 ps_uart6: power-controller@2a0 {
454 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
455 reg = <0x2a0 4>;
456 #power-domain-cells = <0>;
457 #reset-cells = <0>;
458 label = "uart6";
459 power-domains = <&ps_uart_p>;
460 };
461
462 ps_uart7: power-controller@2a8 {
463 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
464 reg = <0x2a8 4>;
465 #power-domain-cells = <0>;
466 #reset-cells = <0>;
467 label = "uart7";
468 power-domains = <&ps_uart_p>;
469 };
470
471 ps_uart8: power-controller@2b0 {
472 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
473 reg = <0x2b0 4>;
474 #power-domain-cells = <0>;
475 #reset-cells = <0>;
476 label = "uart8";
477 power-domains = <&ps_uart_p>;
478 };
479
480 ps_mca0: power-controller@2b8 {
481 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
482 reg = <0x2b8 4>;
483 #power-domain-cells = <0>;
484 #reset-cells = <0>;
485 label = "mca0";
486 power-domains = <&ps_audio_p>, <&ps_sio_adma>, <&ps_mca1>, <&ps_mca2>, <&ps_mca3>, <&ps_mca4>, <&ps_mca5>;
487 };
488
489 ps_mca1: power-controller@2c0 {
490 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
491 reg = <0x2c0 4>;
492 #power-domain-cells = <0>;
493 #reset-cells = <0>;
494 label = "mca1";
495 power-domains = <&ps_audio_p>, <&ps_sio_adma>;
496 };
497
498 ps_mca2: power-controller@2c8 {
499 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
500 reg = <0x2c8 4>;
501 #power-domain-cells = <0>;
502 #reset-cells = <0>;
503 label = "mca2";
504 power-domains = <&ps_audio_p>, <&ps_sio_adma>;
505 };
506
507 ps_mca3: power-controller@2d0 {
508 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
509 reg = <0x2d0 4>;
510 #power-domain-cells = <0>;
511 #reset-cells = <0>;
512 label = "mca3";
513 power-domains = <&ps_audio_p>, <&ps_sio_adma>;
514 };
515
516 ps_mca4: power-controller@2d8 {
517 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
518 reg = <0x2d8 4>;
519 #power-domain-cells = <0>;
520 #reset-cells = <0>;
521 label = "mca4";
522 power-domains = <&ps_audio_p>, <&ps_sio_adma>;
523 };
524
525 ps_mca5: power-controller@2e0 {
526 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
527 reg = <0x2e0 4>;
528 #power-domain-cells = <0>;
529 #reset-cells = <0>;
530 label = "mca5";
531 power-domains = <&ps_audio_p>, <&ps_sio_adma>;
532 };
533
534 ps_dpa0: power-controller@2e8 {
535 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
536 reg = <0x2e8 4>;
537 #power-domain-cells = <0>;
538 #reset-cells = <0>;
539 label = "dpa0";
540 power-domains = <&ps_audio_p>;
541 };
542
543 ps_dpa1: power-controller@2f0 {
544 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
545 reg = <0x2f0 4>;
546 #power-domain-cells = <0>;
547 #reset-cells = <0>;
548 label = "dpa1";
549 power-domains = <&ps_audio_p>;
550 };
551
552 ps_mcc: power-controller@2f8 {
553 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
554 reg = <0x2f8 4>;
555 #power-domain-cells = <0>;
556 #reset-cells = <0>;
557 label = "mcc";
558 apple,always-on; /* Memory controller */
559 };
560
561 ps_spi4: power-controller@260 {
562 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
563 reg = <0x260 4>;
564 #power-domain-cells = <0>;
565 #reset-cells = <0>;
566 label = "spi4";
567 power-domains = <&ps_sio>, <&ps_spi_p>;
568 };
569
570 ps_dcs0: power-controller@300 {
571 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
572 reg = <0x300 4>;
573 #power-domain-cells = <0>;
574 #reset-cells = <0>;
575 label = "dcs0";
576 apple,always-on; /* LPDDR4 interface */
577 };
578
579 ps_dcs1: power-controller@310 {
580 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
581 reg = <0x310 4>;
582 #power-domain-cells = <0>;
583 #reset-cells = <0>;
584 label = "dcs1";
585 apple,always-on; /* LPDDR4 interface */
586 };
587
588 ps_dcs2: power-controller@308 {
589 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
590 reg = <0x308 4>;
591 #power-domain-cells = <0>;
592 #reset-cells = <0>;
593 label = "dcs2";
594 apple,always-on; /* LPDDR4 interface */
595 };
596
597 ps_dcs3: power-controller@318 {
598 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
599 reg = <0x318 4>;
600 #power-domain-cells = <0>;
601 #reset-cells = <0>;
602 label = "dcs3";
603 apple,always-on; /* LPDDR4 interface */
604 };
605
606 ps_smx: power-controller@340 {
607 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
608 reg = <0x340 4>;
609 #power-domain-cells = <0>;
610 #reset-cells = <0>;
611 label = "smx";
612 apple,always-on; /* Apple fabric, critical block */
613 };
614
615 ps_apcie: power-controller@348 {
616 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
617 reg = <0x348 4>;
618 #power-domain-cells = <0>;
619 #reset-cells = <0>;
620 label = "apcie";
621 power-domains = <&ps_imx>, <&ps_pcie_ref>;
622 };
623
624 ps_rmx: power-controller@350 {
625 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
626 reg = <0x350 4>;
627 #power-domain-cells = <0>;
628 #reset-cells = <0>;
629 label = "rmx";
630 /* Apple Fabric, display/image stuff: this can power down */
631 };
632
633 ps_mmx: power-controller@358 {
634 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
635 reg = <0x358 4>;
636 #power-domain-cells = <0>;
637 #reset-cells = <0>;
638 label = "mmx";
639 /* Apple Fabric, media stuff: this can power down */
640 };
641
642 ps_disp0_fe: power-controller@360 {
643 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
644 reg = <0x360 4>;
645 #power-domain-cells = <0>;
646 #reset-cells = <0>;
647 label = "disp0_fe";
648 power-domains = <&ps_rmx>;
649 apple,always-on; /* TODO: figure out if we can enable PM here */
650 };
651
652 ps_dispext_fe: power-controller@368 {
653 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
654 reg = <0x368 4>;
655 #power-domain-cells = <0>;
656 #reset-cells = <0>;
657 label = "dispext_fe";
658 power-domains = <&ps_rmx>;
659 };
660
661 ps_dispext_cpu0: power-controller@378 {
662 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
663 reg = <0x378 4>;
664 #power-domain-cells = <0>;
665 #reset-cells = <0>;
666 label = "dispext_cpu0";
667 power-domains = <&ps_dispext_fe>;
668 apple,min-state = <4>;
669 };
670
671 ps_jpg: power-controller@3c0 {
672 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
673 reg = <0x3c0 4>;
674 #power-domain-cells = <0>;
675 #reset-cells = <0>;
676 label = "jpg";
677 power-domains = <&ps_mmx>;
678 };
679
680 ps_msr: power-controller@3c8 {
681 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
682 reg = <0x3c8 4>;
683 #power-domain-cells = <0>;
684 #reset-cells = <0>;
685 label = "msr";
686 power-domains = <&ps_mmx>;
687 };
688
689 ps_msr_ase_core: power-controller@3d0 {
690 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
691 reg = <0x3d0 4>;
692 #power-domain-cells = <0>;
693 #reset-cells = <0>;
694 label = "msr_ase_core";
695 };
696
697 ps_pmp: power-controller@3d8 {
698 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
699 reg = <0x3d8 4>;
700 #power-domain-cells = <0>;
701 #reset-cells = <0>;
702 label = "pmp";
703 };
704
705 ps_pms_sram: power-controller@3e0 {
706 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
707 reg = <0x3e0 4>;
708 #power-domain-cells = <0>;
709 #reset-cells = <0>;
710 label = "pms_sram";
711 };
712
713 ps_apcie_gp: power-controller@3e8 {
714 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
715 reg = <0x3e8 4>;
716 #power-domain-cells = <0>;
717 #reset-cells = <0>;
718 label = "apcie_gp";
719 power-domains = <&ps_apcie>;
720 };
721
722 ps_ans2: power-controller@3f0 {
723 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
724 reg = <0x3f0 4>;
725 #power-domain-cells = <0>;
726 #reset-cells = <0>;
727 label = "ans2";
728 /*
729 * The ADT makes ps_apcie_st depend on ps_ans2 instead, but this
730 * doesn't make much sense since ANS2 uses APCIE_ST.
731 */
732 power-domains = <&ps_apcie_st>;
733 };
734
735 ps_gfx: power-controller@3f8 {
736 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
737 reg = <0x3f8 4>;
738 #power-domain-cells = <0>;
739 #reset-cells = <0>;
740 label = "gfx";
741 };
742
743 ps_dcs4: power-controller@320 {
744 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
745 reg = <0x320 4>;
746 #power-domain-cells = <0>;
747 #reset-cells = <0>;
748 label = "dcs4";
749 apple,always-on; /* LPDDR4 interface */
750 };
751
752 ps_dcs5: power-controller@330 {
753 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
754 reg = <0x330 4>;
755 #power-domain-cells = <0>;
756 #reset-cells = <0>;
757 label = "dcs5";
758 apple,always-on; /* LPDDR4 interface */
759 };
760
761 ps_dcs6: power-controller@328 {
762 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
763 reg = <0x328 4>;
764 #power-domain-cells = <0>;
765 #reset-cells = <0>;
766 label = "dcs6";
767 apple,always-on; /* LPDDR4 interface */
768 };
769
770 ps_dcs7: power-controller@338 {
771 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
772 reg = <0x338 4>;
773 #power-domain-cells = <0>;
774 #reset-cells = <0>;
775 label = "dcs7";
776 apple,always-on; /* LPDDR4 interface */
777 };
778
779 ps_dispdfr_fe: power-controller@3a8 {
780 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
781 reg = <0x3a8 4>;
782 #power-domain-cells = <0>;
783 #reset-cells = <0>;
784 label = "dispdfr_fe";
785 power-domains = <&ps_rmx>;
786 };
787
788 ps_dispdfr_be: power-controller@3b0 {
789 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
790 reg = <0x3b0 4>;
791 #power-domain-cells = <0>;
792 #reset-cells = <0>;
793 label = "dispdfr_be";
794 power-domains = <&ps_dispdfr_fe>;
795 };
796
797 ps_mipi_dsi: power-controller@3b8 {
798 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
799 reg = <0x3b8 4>;
800 #power-domain-cells = <0>;
801 #reset-cells = <0>;
802 label = "mipi_dsi";
803 power-domains = <&ps_dispdfr_be>;
804 };
805
806 ps_isp_sys: power-controller@400 {
807 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
808 reg = <0x400 4>;
809 #power-domain-cells = <0>;
810 #reset-cells = <0>;
811 label = "isp_sys";
812 power-domains = <&ps_rmx>;
813 };
814
815 ps_venc_sys: power-controller@408 {
816 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
817 reg = <0x408 4>;
818 #power-domain-cells = <0>;
819 #reset-cells = <0>;
820 label = "venc_sys";
821 power-domains = <&ps_mmx>;
822 };
823
824 ps_avd_sys: power-controller@410 {
825 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
826 reg = <0x410 4>;
827 #power-domain-cells = <0>;
828 #reset-cells = <0>;
829 label = "avd_sys";
830 power-domains = <&ps_mmx>;
831 };
832
833 ps_apcie_st: power-controller@418 {
834 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
835 reg = <0x418 4>;
836 #power-domain-cells = <0>;
837 #reset-cells = <0>;
838 label = "apcie_st";
839 power-domains = <&ps_apcie>;
840 };
841
842 ps_ane_sys: power-controller@470 {
843 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
844 reg = <0x470 4>;
845 #power-domain-cells = <0>;
846 #reset-cells = <0>;
847 label = "ane_sys";
848 };
849
850 ps_atc0_common: power-controller@420 {
851 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
852 reg = <0x420 4>;
853 #power-domain-cells = <0>;
854 #reset-cells = <0>;
855 label = "atc0_common";
856 };
857
858 ps_atc0_pcie: power-controller@428 {
859 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
860 reg = <0x428 4>;
861 #power-domain-cells = <0>;
862 #reset-cells = <0>;
863 label = "atc0_pcie";
864 power-domains = <&ps_atc0_common>;
865 };
866
867 ps_atc0_cio: power-controller@430 {
868 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
869 reg = <0x430 4>;
870 #power-domain-cells = <0>;
871 #reset-cells = <0>;
872 label = "atc0_cio";
873 power-domains = <&ps_atc0_common>;
874 };
875
876 ps_atc0_cio_pcie: power-controller@438 {
877 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
878 reg = <0x438 4>;
879 #power-domain-cells = <0>;
880 #reset-cells = <0>;
881 label = "atc0_cio_pcie";
882 power-domains = <&ps_atc0_cio>;
883 };
884
885 ps_atc0_cio_usb: power-controller@440 {
886 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
887 reg = <0x440 4>;
888 #power-domain-cells = <0>;
889 #reset-cells = <0>;
890 label = "atc0_cio_usb";
891 power-domains = <&ps_atc0_cio>;
892 };
893
894 ps_atc1_common: power-controller@448 {
895 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
896 reg = <0x448 4>;
897 #power-domain-cells = <0>;
898 #reset-cells = <0>;
899 label = "atc1_common";
900 };
901
902 ps_atc1_pcie: power-controller@450 {
903 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
904 reg = <0x450 4>;
905 #power-domain-cells = <0>;
906 #reset-cells = <0>;
907 label = "atc1_pcie";
908 power-domains = <&ps_atc1_common>;
909 };
910
911 ps_atc1_cio: power-controller@458 {
912 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
913 reg = <0x458 4>;
914 #power-domain-cells = <0>;
915 #reset-cells = <0>;
916 label = "atc1_cio";
917 power-domains = <&ps_atc1_common>;
918 };
919
920 ps_atc1_cio_pcie: power-controller@460 {
921 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
922 reg = <0x460 4>;
923 #power-domain-cells = <0>;
924 #reset-cells = <0>;
925 label = "atc1_cio_pcie";
926 power-domains = <&ps_atc1_cio>;
927 };
928
929 ps_atc1_cio_usb: power-controller@468 {
930 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
931 reg = <0x468 4>;
932 #power-domain-cells = <0>;
933 #reset-cells = <0>;
934 label = "atc1_cio_usb";
935 power-domains = <&ps_atc1_cio>;
936 };
937
938 ps_sep: power-controller@c00 {
939 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
940 reg = <0xc00 4>;
941 #power-domain-cells = <0>;
942 #reset-cells = <0>;
943 label = "sep";
944 apple,always-on; /* Locked on */
945 };
946
947 ps_venc_dma: power-controller@8000 {
948 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
949 reg = <0x8000 4>;
950 #power-domain-cells = <0>;
951 #reset-cells = <0>;
952 label = "venc_dma";
953 power-domains = <&ps_venc_sys>;
954 };
955
956 ps_venc_pipe4: power-controller@8008 {
957 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
958 reg = <0x8008 4>;
959 #power-domain-cells = <0>;
960 #reset-cells = <0>;
961 label = "venc_pipe4";
962 power-domains = <&ps_venc_dma>;
963 };
964
965 ps_venc_pipe5: power-controller@8010 {
966 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
967 reg = <0x8010 4>;
968 #power-domain-cells = <0>;
969 #reset-cells = <0>;
970 label = "venc_pipe5";
971 power-domains = <&ps_venc_dma>;
972 };
973
974 ps_venc_me0: power-controller@8018 {
975 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
976 reg = <0x8018 4>;
977 #power-domain-cells = <0>;
978 #reset-cells = <0>;
979 label = "venc_me0";
980 power-domains = <&ps_venc_pipe4>, <&ps_venc_pipe5>;
981 };
982
983 ps_venc_me1: power-controller@8020 {
984 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
985 reg = <0x8020 4>;
986 #power-domain-cells = <0>;
987 #reset-cells = <0>;
988 label = "venc_me1";
989 power-domains = <&ps_venc_pipe4>, <&ps_venc_pipe5>;
990 };
991
992 ps_ane_sys_cpu: power-controller@c000 {
993 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
994 reg = <0xc000 4>;
995 #power-domain-cells = <0>;
996 #reset-cells = <0>;
997 label = "ane_sys_cpu";
998 power-domains = <&ps_ane_sys>;
999 };
1000
1001 ps_disp0_cpu0: power-controller@10018 {
1002 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
1003 reg = <0x10018 4>;
1004 #power-domain-cells = <0>;
1005 #reset-cells = <0>;
1006 label = "disp0_cpu0";
1007 power-domains = <&ps_disp0_fe>;
1008 apple,always-on; /* TODO: figure out if we can enable PM here */
1009 apple,min-state = <4>;
1010 };
1011};
1012
1013&pmgr_mini {
1014 ps_debug: power-controller@58 {
1015 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
1016 reg = <0x58 4>;
1017 #power-domain-cells = <0>;
1018 #reset-cells = <0>;
1019 label = "debug";
1020 apple,always-on; /* Core AON device */
1021 };
1022
1023 ps_nub_spmi0: power-controller@60 {
1024 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
1025 reg = <0x60 4>;
1026 #power-domain-cells = <0>;
1027 #reset-cells = <0>;
1028 label = "nub_spmi0";
1029 apple,always-on; /* Core AON device */
1030 };
1031
1032 ps_nub_aon: power-controller@70 {
1033 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
1034 reg = <0x70 4>;
1035 #power-domain-cells = <0>;
1036 #reset-cells = <0>;
1037 label = "nub_aon";
1038 apple,always-on; /* Core AON device */
1039 };
1040
1041 ps_nub_gpio: power-controller@80 {
1042 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
1043 reg = <0x80 4>;
1044 #power-domain-cells = <0>;
1045 #reset-cells = <0>;
1046 label = "nub_gpio";
1047 apple,always-on; /* Core AON device */
1048 };
1049
1050 ps_nub_fabric: power-controller@a8 {
1051 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
1052 reg = <0xa8 4>;
1053 #power-domain-cells = <0>;
1054 #reset-cells = <0>;
1055 label = "nub_fabric";
1056 apple,always-on; /* Core AON device */
1057 };
1058
1059 ps_nub_sram: power-controller@b0 {
1060 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
1061 reg = <0xb0 4>;
1062 #power-domain-cells = <0>;
1063 #reset-cells = <0>;
1064 label = "nub_sram";
1065 apple,always-on; /* Core AON device */
1066 };
1067
1068 ps_debug_usb: power-controller@b8 {
1069 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
1070 reg = <0xb8 4>;
1071 #power-domain-cells = <0>;
1072 #reset-cells = <0>;
1073 label = "debug_usb";
1074 apple,always-on; /* Core AON device */
1075 power-domains = <&ps_debug>;
1076 };
1077
1078 ps_debug_auth: power-controller@c0 {
1079 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
1080 reg = <0xc0 4>;
1081 #power-domain-cells = <0>;
1082 #reset-cells = <0>;
1083 label = "debug_auth";
1084 apple,always-on; /* Core AON device */
1085 power-domains = <&ps_debug>;
1086 };
1087
1088 ps_nub_spmi1: power-controller@68 {
1089 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
1090 reg = <0x68 4>;
1091 #power-domain-cells = <0>;
1092 #reset-cells = <0>;
1093 label = "nub_spmi1";
1094 apple,always-on; /* Core AON device */
1095 };
1096
1097 ps_msg: power-controller@78 {
1098 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
1099 reg = <0x78 4>;
1100 #power-domain-cells = <0>;
1101 #reset-cells = <0>;
1102 label = "msg";
1103 };
1104
1105 ps_atc0_usb_aon: power-controller@88 {
1106 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
1107 reg = <0x88 4>;
1108 #power-domain-cells = <0>;
1109 #reset-cells = <0>;
1110 label = "atc0_usb_aon";
1111 };
1112
1113 ps_atc1_usb_aon: power-controller@90 {
1114 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
1115 reg = <0x90 4>;
1116 #power-domain-cells = <0>;
1117 #reset-cells = <0>;
1118 label = "atc1_usb_aon";
1119 };
1120
1121 ps_atc0_usb: power-controller@98 {
1122 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
1123 reg = <0x98 4>;
1124 #power-domain-cells = <0>;
1125 #reset-cells = <0>;
1126 label = "atc0_usb";
1127 power-domains = <&ps_atc0_usb_aon>, <&ps_atc0_common>;
1128 };
1129
1130 ps_atc1_usb: power-controller@a0 {
1131 compatible = "apple,t8103-pmgr-pwrstate", "apple,pmgr-pwrstate";
1132 reg = <0xa0 4>;
1133 #power-domain-cells = <0>;
1134 #reset-cells = <0>;
1135 label = "atc1_usb";
1136 power-domains = <&ps_atc1_usb_aon>, <&ps_atc1_common>;
1137 };
1138};