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wdenkf7d15722004-12-18 22:35:43 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2000-2005
wdenkf7d15722004-12-18 22:35:43 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC860 1
37#define CONFIG_MPC860T 1
38#define CONFIG_MPC862 1 /* enable 862 since the */
39#define CONFIG_MPC857 1 /* 857 is a variant of the 862 */
40
41#define CONFIG_UC100 1 /* ...on a UC100 module */
42
43#define MPC8XX_FACT 4 /* Multiply by 4 */
44#define MPC8XX_XIN 25000000 /* 25.0 MHz in */
45#define CONFIG_8xx_GCLK_FREQ (MPC8XX_FACT * MPC8XX_XIN)
46 /* define if cant' use get_gclk_freq */
47
48#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
49#undef CONFIG_8xx_CONS_SMC2
50#undef CONFIG_8xx_CONS_NONE
51
52#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
53
54#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
55
56#define CONFIG_BOOTCOUNT_LIMIT
57
58#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
59
60#define CONFIG_BOARD_TYPES 1 /* support board types */
61
62#define CONFIG_PREBOOT "echo;" \
63 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
64 "echo"
65
66#undef CONFIG_BOOTARGS
67
68#define CONFIG_EXTRA_ENV_SETTINGS \
69 "netdev=eth0\0" \
70 "nfsargs=setenv bootargs root=/dev/nfs rw " \
71 "nfsroot=$(serverip):$(rootpath)\0" \
72 "ramargs=setenv bootargs root=/dev/ram rw\0" \
73 "addip=setenv bootargs $(bootargs) " \
74 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
75 ":$(hostname):$(netdev):off panic=1\0" \
76 "addtty=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)\0"\
77 "flash_nfs=run nfsargs addip addtty;" \
78 "bootm $(kernel_addr)\0" \
79 "flash_self=run ramargs addip addtty;" \
80 "bootm $(kernel_addr) $(ramdisk_addr)\0" \
81 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip addtty;" \
82 "bootm\0" \
83 "rootpath=/opt/eldk/ppc_8xx\0" \
84 "bootfile=/tftpboot/uc100/uImage\0" \
85 "kernel_addr=40000000\0" \
86 "ramdisk_addr=40100000\0" \
87 "load=tftp 100000 /tftpboot/uc100/u-boot.bin\0" \
88 "update=protect off 40700000 4073ffff;era 40700000 4073ffff;" \
89 "cp.b 100000 40700000 $(filesize);" \
90 "setenv filesize;saveenv\0" \
91 ""
92#define CONFIG_BOOTCOMMAND "run flash_self"
93
94#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
95#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
96
97#undef CONFIG_WATCHDOG /* watchdog disabled */
98
99#undef CONFIG_STATUS_LED /* no status-led */
100
101#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
102
103#define CONFIG_MAC_PARTITION
104#define CONFIG_DOS_PARTITION
105
106#undef CONFIG_RTC_MPC8xx
107#define CFG_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */
108#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
109
110/*
111 * Power On Self Test support
112 */
113#define CONFIG_POST ( CFG_POST_CACHE | \
114 CFG_POST_MEMORY | \
115 CFG_POST_CPU | \
116 CFG_POST_UART | \
117 CFG_POST_SPR )
118#undef CONFIG_POST
119
120#ifdef CONFIG_POST
121#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
122#else
123#define CFG_CMD_POST_DIAG 0
124#endif
125
126#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
127 CFG_CMD_ASKENV | \
wdenkf7d15722004-12-18 22:35:43 +0000128 CFG_CMD_DATE | \
wdenk414eec32005-04-02 22:37:54 +0000129 CFG_CMD_DHCP | \
130 CFG_CMD_EEPROM | \
131 CFG_CMD_ELF | \
132 CFG_CMD_FAT | \
133 CFG_CMD_I2C | \
134 CFG_CMD_IDE | \
135 CFG_CMD_MII | \
136 CFG_CMD_NFS | \
137 CFG_CMD_PING | \
138 CFG_CMD_POST_DIAG | \
139 CFG_CMD_SNTP )
wdenkf7d15722004-12-18 22:35:43 +0000140
141#define CONFIG_NETCONSOLE
142
143/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
144#include <cmd_confdefs.h>
145
146/*
147 * Miscellaneous configurable options
148 */
149#define CFG_LONGHELP /* undef to save memory */
150#define CFG_PROMPT "=> " /* Monitor Command Prompt */
151
152#if 0
153#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
154#endif
155#ifdef CFG_HUSH_PARSER
156#define CFG_PROMPT_HUSH_PS2 "> "
157#endif
158
159#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
160#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
161#else
162#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
163#endif
164#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
165#define CFG_MAXARGS 16 /* max number of command args */
166#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
167
168#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
169#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
170
171#define CFG_LOAD_ADDR 0x100000 /* default load address */
172
173#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
174
175#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
176
177#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
178
179/*
180 * Low Level Configuration Settings
181 * (address mappings, register initial values, etc.)
182 * You should know what you are doing if you make changes here.
183 */
184/*-----------------------------------------------------------------------
185 * Internal Memory Mapped Register
186 */
187#define CFG_IMMR 0xF0000000
188
189/*-----------------------------------------------------------------------
190 * Definitions for initial stack pointer and data area (in DPRAM)
191 */
192#define CFG_INIT_RAM_ADDR CFG_IMMR
193#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
194#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
195#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
196#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
197
198/*-----------------------------------------------------------------------
199 * Start addresses for the final memory configuration
200 * (Set up by the startup code)
201 * Please note that CFG_SDRAM_BASE _must_ start at 0
202 */
203#define CFG_SDRAM_BASE 0x00000000
204#define CFG_FLASH_BASE 0x40000000
205#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
206#define CFG_MONITOR_BASE (CFG_FLASH_BASE+0x00700000) /* resetvec fff00100*/
207#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
208
209/*-----------------------------------------------------------------------
210 * Address accessed to reset the board - must not be mapped/assigned
211 */
212#define CFG_RESET_ADDRESS 0x90000000
213
214/*
215 * For booting Linux, the board info and command line data
216 * have to be in the first 8 MB of memory, since this is
217 * the maximum mapped by the Linux kernel during initialization.
218 */
219#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
220
221/*-----------------------------------------------------------------------
222 * FLASH organization
223 */
224#define CFG_FLASH_CFI /* The flash is CFI compatible */
225#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
226#define CFG_FLASH_CFI_AMD_RESET 1 /* AMD RESET for STM 29W320DB! */
227
228#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
229#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
230
231#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
232#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
233
234#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
235
236#define CFG_ENV_IS_IN_FLASH 1
237#define CFG_ENV_ADDR (CFG_MONITOR_BASE+CFG_MONITOR_LEN)
238#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
239#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
240
241/* Address and size of Redundant Environment Sector */
242#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR+CFG_ENV_SECT_SIZE)
243#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
244
245/*-----------------------------------------------------------------------
246 * Cache Configuration
247 */
248#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
249#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
250#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
251#endif
252
253/*-----------------------------------------------------------------------
254 * SYPCR - System Protection Control 11-9
255 * SYPCR can only be written once after reset!
256 *-----------------------------------------------------------------------
257 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
258 */
259#if defined(CONFIG_WATCHDOG)
260#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
261 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
262#else
263#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
264#endif
265
266/*-----------------------------------------------------------------------
267 * SIUMCR - SIU Module Configuration 11-6
268 *-----------------------------------------------------------------------
269 * PCMCIA config., multi-function pin tri-state
270 */
271#define CFG_SIUMCR (SIUMCR_FRC | SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
272
273/*-----------------------------------------------------------------------
274 * TBSCR - Time Base Status and Control 11-26
275 *-----------------------------------------------------------------------
276 * Clear Reference Interrupt Status, Timebase freezing enabled
277 */
278#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
279
280/*-----------------------------------------------------------------------
281 * RTCSC - Real-Time Clock Status and Control Register 11-27
282 *-----------------------------------------------------------------------
283 */
284#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
285
286/*-----------------------------------------------------------------------
287 * PISCR - Periodic Interrupt Status and Control 11-31
288 *-----------------------------------------------------------------------
289 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
290 */
291#define CFG_PISCR (PISCR_PS | PISCR_PITF)
292
293/*-----------------------------------------------------------------------
294 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
295 *-----------------------------------------------------------------------
296 * Reset PLL lock status sticky bit, timer expired status bit and timer
297 * interrupt status bit
298 */
299#define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
300 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
301
302/*-----------------------------------------------------------------------
303 * SCCR - System Clock and reset Control Register 15-27
304 *-----------------------------------------------------------------------
305 * Set clock output, timebase and RTC source and divider,
306 * power management and some other internal clocks
307 */
308#define SCCR_MASK 0x00000000
309#define CFG_SCCR (SCCR_EBDF11)
310
311/*-----------------------------------------------------------------------
312 * PCMCIA stuff
313 *-----------------------------------------------------------------------
314 *
315 */
316#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
317#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
318#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
319#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
320#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
321#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
322#define CFG_PCMCIA_IO_ADDR (0xEC000000)
323#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
324
325/*-----------------------------------------------------------------------
326 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
327 *-----------------------------------------------------------------------
328 */
329
330#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
331
332#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
333#undef CONFIG_IDE_LED /* LED for ide not supported */
334#undef CONFIG_IDE_RESET /* reset for ide not supported */
335
336#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
337#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
338
339#define CFG_ATA_IDE0_OFFSET 0x0000
340
341#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
342
343/* Offset for data I/O */
344#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
345
346/* Offset for normal register accesses */
347#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
348
349/* Offset for alternate registers */
350#define CFG_ATA_ALT_OFFSET 0x0100
351
352/*-----------------------------------------------------------------------
353 *
354 *-----------------------------------------------------------------------
355 *
356 */
357#define CFG_DER 0
358
359/*
360 * Init Memory Controller:
361 *
362 * BR0/1 and OR0/1 (FLASH)
363 */
364
365#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
366#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
367
368/* used to re-map FLASH both when starting from SRAM or FLASH:
369 * restrict access enough to keep SRAM working (if any)
370 * but not too much to meddle with FLASH accesses
371 */
372#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
373#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
374
375/*
376 * FLASH timing:
377 */
378#define CFG_OR_TIMING_FLASH (0x00000d24)
379
380#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
381#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
382#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
383
384#define CFG_BR1_PRELIM 0x00000081 /* Chip select for SDRAM (32 Bit, UPMA) */
385#define CFG_OR1_PRELIM 0xfc000a00
386#define CFG_BR2_PRELIM 0x80000001 /* Chip select for SRAM (32 Bit, GPCM) */
387#define CFG_OR2_PRELIM 0xfff00d24
388#define CFG_BR3_PRELIM 0x80600401 /* Chip select for Display (8 Bit, GPCM) */
389#define CFG_OR3_PRELIM 0xffff8f44
390#define CFG_BR4_PRELIM 0xc05108c1 /* Chip select for Interbus MPM (16 Bit, UPMB) */
391#define CFG_OR4_PRELIM 0xffff0300
392#define CFG_BR5_PRELIM 0xc0500401 /* Chip select for Interbus Status (8 Bit, GPCM) */
393#define CFG_OR5_PRELIM 0xffff8db0
394
395/*
396 * Memory Periodic Timer Prescaler
397 *
398 * The Divider for PTA (refresh timer) configuration is based on an
399 * example SDRAM configuration (64 MBit, one bank). The adjustment to
400 * the number of chip selects (NCS) and the actually needed refresh
401 * rate is done by setting MPTPR.
402 *
403 * PTA is calculated from
404 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
405 *
406 * gclk CPU clock (not bus clock!)
407 * Trefresh Refresh cycle * 4 (four word bursts used)
408 *
409 * 4096 Rows from SDRAM example configuration
410 * 1000 factor s -> ms
411 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
412 * 4 Number of refresh cycles per period
413 * 64 Refresh cycle in ms per number of rows
414 * --------------------------------------------
415 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
416 *
417 * 50 MHz => 50.000.000 / Divider = 98
418 * 66 Mhz => 66.000.000 / Divider = 129
419 * 80 Mhz => 80.000.000 / Divider = 156
420 * 100 Mhz => 100.000.000 / Divider = 195
421 */
422
423#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
424#define CFG_MAMR_PTA 98
425
426/*
427 * For 16 MBit, refresh rates could be 31.3 us
428 * (= 64 ms / 2K = 125 / quad bursts).
429 * For a simpler initialization, 15.6 us is used instead.
430 *
431 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
432 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
433 */
434#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
435#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
436
437/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
438#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
439#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
440
441/*
442 * MAMR settings for SDRAM
443 */
444
445/* 8 column SDRAM */
446#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
447 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
448 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
449/* 9 column SDRAM */
450#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
451 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
452 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
453
454#define CFG_MAMR_VAL 0x30904114 /* for SDRAM */
455#define CFG_MBMR_VAL 0xff001111 /* for Interbus-MPM */
456
457/*-----------------------------------------------------------------------
458 * I2C stuff
459 */
460
461/* enable I2C and select the hardware/software driver */
462#undef CONFIG_HARD_I2C /* I2C with hardware support */
463#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
464
465#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */
466#define CFG_I2C_SLAVE 0xFE
467
468#ifdef CONFIG_SOFT_I2C
469/*
470 * Software (bit-bang) I2C driver configuration
471 */
472#define PB_SCL 0x00000020 /* PB 26 */
473#define PB_SDA 0x00000010 /* PB 27 */
474
475#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
476#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
477#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
478#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
479#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
480 else immr->im_cpm.cp_pbdat &= ~PB_SDA
481#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
482 else immr->im_cpm.cp_pbdat &= ~PB_SCL
483#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
484#endif /* CONFIG_SOFT_I2C */
485
486/*-----------------------------------------------------------------------
487 * I2C EEPROM (24C164)
488 */
489#define CFG_I2C_EEPROM_ADDR 0x58 /* EEPROM AT24C164 */
490#define CFG_I2C_EEPROM_ADDR_LEN 1
491#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
492#define CFG_EEPROM_PAGE_WRITE_BITS 4
493
494/*
495 * Internal Definitions
496 *
497 * Boot Flags
498 */
499#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
500#define BOOTFLAG_WARM 0x02 /* Software reboot */
501
502#define CONFIG_FEC_ENET 1 /* use FEC ethernet */
503#define FEC_ENET
504#define CONFIG_MII
505#define CFG_DISCOVER_PHY 1
506
507#endif /* __CONFIG_H */