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wdenkefee1702002-07-20 20:14:13 +00001/*
2 * Copyright (C) 2000 Murray Jensen <Murray.Jensen@cmst.csiro.au>
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
wdenkefee1702002-07-20 20:14:13 +00005 */
6
7#include <config.h>
8#include <command.h>
9#include <mpc8xx.h>
10#include <version.h>
11
wdenkefee1702002-07-20 20:14:13 +000012#include <ppc_asm.tmpl>
13#include <ppc_defs.h>
14
15#include <asm/cache.h>
16#include <asm/mmu.h>
17
Jon Loeliger44312832007-07-09 19:06:00 -050018#if defined(CONFIG_CMD_KGDB)
wdenkefee1702002-07-20 20:14:13 +000019
20 /*
21 * cache flushing routines for kgdb
22 */
23
24 .globl kgdb_flush_cache_all
25kgdb_flush_cache_all:
26 lis r3, IDC_INVALL@h
27 mtspr DC_CST, r3
28 sync
29 lis r3, IDC_INVALL@h
30 mtspr IC_CST, r3
31 SYNC
32 blr
33
34 .globl kgdb_flush_cache_range
35kgdb_flush_cache_range:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020036 li r5,CONFIG_SYS_CACHELINE_SIZE-1
wdenkefee1702002-07-20 20:14:13 +000037 andc r3,r3,r5
38 subf r4,r3,r4
39 add r4,r4,r5
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020040 srwi. r4,r4,CONFIG_SYS_CACHELINE_SHIFT
wdenkefee1702002-07-20 20:14:13 +000041 beqlr
42 mtctr r4
43 mr r6,r3
441: dcbst 0,r3
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020045 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
wdenkefee1702002-07-20 20:14:13 +000046 bdnz 1b
47 sync /* wait for dcbst's to get to ram */
48 mtctr r4
492: icbi 0,r6
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020050 addi r6,r6,CONFIG_SYS_CACHELINE_SIZE
wdenkefee1702002-07-20 20:14:13 +000051 bdnz 2b
52 SYNC
53 blr
54
Jon Loeliger068b60a2007-07-10 10:27:39 -050055#endif